We are hiring an STA/Synthesis Engineer to join our VLSI delivery team. You will own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout.
Key Responsibilities:
- Logic-aware synthesis, logical equivalence checks (LEC), and VCLP signoff
- SDC and UPF constraint development, including DFT-aware constraints
- Pre- and post-layout timing closure across corners and modes
- Manual ECO generation to resolve timing and DRC violations
- Timing closure at block, subsystem and full-chip level
- Lead and mentor a team of 4-5 engineers on STA/Synthesis practices
- Partner closely with RTL design and Physical Design teams on SoC timing closure
Requirements:
- 4+ years of hands-on experience in STA and Synthesis
- Strong TCL scripting and Unix environment skills
- Comprehensive knowledge of timing signoff flows and constraint development
Skills Required
- At least 4 years of hands-on experience in static timing analysis and synthesis
- Strong TCL scripting skills
- Strong Unix environment skills
- Comprehensive knowledge of timing signoff flows
- Experience with constraint development, including SDC, UPF, and DFT-aware constraints
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