Sr. Staff RTL Eng

Posted One Month Ago
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Pune, Maharashtra, IND
In-Office
Senior level
Semiconductor • Manufacturing
The Role
Design and develop RTL for low-power FPGA machine-learning engines, optimize datapaths for high throughput and low latency, implement ML operators (e.g., convolution), collaborate with algorithm and architecture teams, perform functional simulation and synthesis, and achieve timing closure for ML accelerators.
Summary Generated by Built In
Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Job Description:

Lattice Overview

Lattice Semiconductor (NASDAQ: LSCC) is the global leader in smart connectivity solutions, providing market leading intellectual property and low-power, small form-factor devices that enable more than 8,000 global customers to quickly deliver innovative and differentiated cost and power efficient products.

The Company's broad, end-market exposure solves customer problems across the network from the Edge to the Cloud for clients in consumer electronics, industrial equipment, communications infrastructure, computing and automotive. Our technology, long-standing relationships and commitment to world-class support enables our customers to quickly and easily unleash innovative solutions to create a smart, secure and connected world.

Our control, connect and compute solutions enable the Internet of Things to operate safely, easily and more autonomously at the edge of the network core. While you may not see our products, you are interacting with them all day, every day. We make your experience smarter and better-connected. Join Team Lattice…and help us continue to drive innovation that creates a smarter, better-connected world. Together, we enable what’s next.

Responsibilities & Skill

sensAI team at Lattice Semiconductor, innovates and creates solutions to enable edgeAI with programmable low power devices. Our vision is to unleash FPGA to add intelligence to every sensor used in Automotive, industrial and consumer products. As a senior member of the team, you will be responsible for developing and enhancing machine learning engine that infers neural networks on resource constrained devices. You need to bring expertise in machine learning to enable computer vision, robotics, human-machine interaction, or other related domains.

Job Description

We are seeking a highly motivated Senior Staff design engineer who will be responsible for design and development of RTL for Machine Learning engine.  You are responsible to implement ML operators efficiently using resources on low power FPGA. You need to bring experience in optimizing data path for high throughput and low latency. Good understanding of neural network accelerators and/or DSP processors is essential to be successful in this job.

Requirements

Key Skills

  • In-depth experience in designing and developing RTL using Verilog, System Verilog-HDL.
  • Ability to carry out functional simulation using industry standard simulation tools such as Xcelium-Cadence, VCS-Synopsys.
  • Good understanding of ML operations like convolution.
  • Architect and design RTL for Machine Learning compute engines targeting low‑power FPGA platforms.
  • Collaborate with algorithm and architecture teams to translate ML models/operators into efficient hardware micro‑architectures.
  • Experience in image processing and DSP algorithms implementation
  • Deep understanding of machine learning, data models to optimally map it with hardware.
  • Experience in FPGA/ASIC synthesis flow, timing closure.
  • Working knowledge of computer architecture and memory management.
  • Experience with C and/or SystemC is a plus

Education and General:

  • BE/MTech/PhD in Electronics, Electrical or Computer Engineering
  • Minimum of 14 years (12 years for MTech and 8 years for PHD) experience in RTL design
  • Independent and self-motivated, capable of executing under dynamic environment and uncertainties
  • Innovative, problem solver who likes to come up with newer and better solutions for existing problems
  • Good cross team communication and technical documentation desired

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

India

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. 


Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit 
www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.

 

Skills Required

  • In-depth experience designing and developing RTL using Verilog and SystemVerilog
  • Functional simulation using industry-standard tools (Xcelium - Cadence, VCS - Synopsys)
  • Good understanding of ML operations such as convolution and mapping ML models to hardware
  • Architect and design RTL for machine learning compute engines targeting low-power FPGA platforms
  • Experience in image processing and DSP algorithms implementation
  • Deep understanding of machine learning and data models for optimal hardware mapping
  • Experience with FPGA/ASIC synthesis flow and timing closure
  • Working knowledge of computer architecture and memory management
  • Experience with C and/or SystemC
  • BE/MTech/PhD in Electronics, Electrical, or Computer Engineering
  • Minimum of 14 years (12 for MTech, 8 for PhD) experience in RTL design
  • Strong independent execution, problem solving, cross-team communication, and technical documentation skills
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The Company
HQ: Hillsboro, OR
975 Employees
Year Founded: 1983

What We Do

Lattice Semiconductor (NASDAQ: LSCC) is the low power programmable leader. We solve customer problems across the network, from the Edge to the Cloud, in the growing communications, computing, industrial, automotive and consumer markets. Our technology, long-standing relationships, and commitment to world-class support lets our customers quickly and easily unleash their innovation to create a smart, secure and connected world. Lattice was founded in 1983 and is headquartered in Hillsboro, Oregon with major operations in San Jose, California, Shanghai, China, and Manila, Philippines.

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