As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
About the Role:
We are seeking a highly experienced Senior Staff Power Integrity Engineer to serve as the primary technical authority and owner for all IR drop and power delivery aspects of our high-speed CPUs. In this role, you will define sign-off criteria, drive advanced power analysis methodologies, and spearhead the automation of power and IR flows to ensure highly efficient, robust power delivery networks for high-performance compute architectures.
Key Responsibilities
Technical Leadership: Act as the primary point of contact and subject matter expert for dynamic and static IR signoff criteria across the high-speed CPU design team.
Power Delivery Architecture: Architect highly efficient, power-density-aware Power Grid (PG) designs and optimize bump maps based on rigorous power density requirements.
IR Flow Automation: Spearhead the IR drop analysis flow. Collaborate closely with the Physical Design (PD) and Power teams to automate and streamline static and dynamic IR readouts.
Power Readout Integration: Lead the PrimeTime-PX (PTPX) flow development, partnering with cross-functional teams to seamlessly automate accurate power readouts.
Required Qualifications
IR Signoff & Tools: Deep, authoritative understanding of dynamic and static IR signoff, including defining pass/fail criteria and margins. Expertise with Ansys tools (e.g., RedHawk) is a must.
Grid & Bump Design: Deep, hands-on experience with PG grid design and bump placement methodologies driven by complex power density limits.
Power Analysis: Strong working understanding of PTPX for vector-driven and vectorless power readouts.
CPU Implementation: Proven experience driving power integrity closure specifically for high-speed CPU architectures.
Physical Design Flow: Solid foundational understanding of the Physical Design flow, with specific expertise in low power implementation techniques and methodologies.
Experience: 10+ years of experience in Physical Design with a minimum qualification of bachelor's or master's degree.
Preferred Qualifications
Advanced Packaging: Hands-on experience with 3D IC design and package-silicon co-design is highly preferred.
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
IndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Skills Required
- Deep understanding of dynamic and static IR signoff, including defining pass/fail criteria and margins
- Expertise with Ansys tools (e.g., RedHawk)
- Hands-on experience with Power Grid (PG) design and bump placement methodologies driven by complex power density limits
- Working understanding of PrimeTime-PX (PTPX) for vector-driven and vectorless power readouts
- Proven experience driving power integrity closure for high-speed CPU architectures
- Foundational understanding of the Physical Design flow and expertise in low-power implementation techniques
- 10+ years of experience in Physical Design and a minimum of a bachelor's or master's degree
- Hands-on experience with 3D IC design and package-silicon co-design
What We Do
The heart of SiFive is RISC-V! SiFive creates the building blocks of RISC-V-based IP that are the inevitable innovative reimagining of every computing platform.
