(Sr.) Staff Engineer, Digital IC Design

Reposted Yesterday
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Hsinchu County, TWN
In-Office
Senior level
Artificial Intelligence • Automotive • Semiconductor
We create custom semiconductor solutions that move, process, store, and secure data quickly and reliably.
The Role
The Staff Engineer will design and verify digital circuits for high-speed data communication ICs, including developing verification plans, collaborating with cross-functional teams, and performing test integration.
Summary Generated by Built In

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell Central Engineering (CE) develops Marvell's most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Automotive, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system. Central System Engineering (CSE) in Central Engineering, independent of other CE functions including DSP algorithm development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs in the lab environment and supporting all Marvell business units for fast and smooth SoC production. Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.

What You Can Expect

ASIC design engineer responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in verification plan
development, test environment setup, modeling, testcase development and execution. He/She will be responsible for block and/or chip level verification.
The responsibilities include but not limited to.
  • Improve the design methodology and flow.
  • Design and verification for various types of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications.
  • Collaborate with Analog/DSP/Digital Design/FW/AE teams to deliver the competitive SerDes IP solutions for all the Marvell product lines.
  • Provide the support to the product teams, for both pre and post silicon
  • Test chip integration

    What We're Looking For

    * Master’s degree and/or PhD in EE, CS or related fields and 3+ years of experience.
    * Good personal communication skills and team working spirit.
    * Hardworking and motivated to be part of a highly competent design team.
    Must be proficient in the following skills:
    • Fundamental concepts in digital logic design
    • Understand ASIC verification flows and methodologies
    • Verilog and SystemVerilog/SystemC/Vera
    • Strong Perl and Tcl scripting
    • UNIX Shell scripting (Csh, Bash)

    Highly desirable skills:
    • Formal verification
    • Low power design
    • MATLAB and C/C++ based system simulation and evaluation
    • DSP function hardware implementation knowledge

    Additional Compensation and Benefit Elements

    With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

    All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

    Interview Integrity 

    To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

    These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

    This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

    #LI-SYU

    Skills Required

    • Master's degree and/or PhD in EE, CS or related fields
    • 3+ years of experience
    • Proficiency in digital logic design
    • Understanding of ASIC verification flows and methodologies
    • Strong Perl and Tcl scripting
    • UNIX Shell scripting (Csh, Bash)

    Marvell Technology Compensation & Benefits Highlights

    The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Marvell Technology and has not been reviewed or approved by Marvell Technology.

    • Equity Value & Accessibility Equity appears to be a meaningful part of total rewards through RSUs and an ESPP with a 15% discount and lookback, which can materially raise overall compensation. Stock upside is positioned as a key differentiator when company performance is strong.
    • Parental & Family Support Paid parental/bonding leave is described as substantial, with additional disability leave for birthing parents and a flexible return-to-work program. Family-care leave, generous bereavement provisions, and family-building support (e.g., adoption/surrogacy reimbursement) further strengthen the package.
    • Healthcare Strength Medical coverage is presented as broad with multiple plan options and preventive care covered at 100% in-network, alongside dental, vision, and structured mental-health support. Additional programs like telehealth and specialized care partners add depth to the health offering.

    Marvell Technology Insights

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    The Company
    HQ: Santa Clara, CA
    6,500 Employees
    Year Founded: 1995

    What We Do

    Marvell specializes in semiconductor solutions that power a wide range of industries, from data centers and 5G networks to AI, automotive, and storage applications. Our cutting-edge products are designed to meet the constantly evolving demands of a connected world, enabling faster, more efficient and more secure data processing and communication. With a focus on excellence and a commitment to advancing technology, we develop solutions that drive progress and transform industries.

    Why Work With Us

    Life at Marvell means being a part of new innovation and enduring technology; but it's also much more. Our diverse community is strengthened through cultural events, corporate gatherings and team-building activities, fostering collaboration and making work enjoyable. At Marvell, it's not just a job; it's an enriching, community-driven experience.

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