About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell’s Optical DSP (ODSP) team within the Connectivity Business Unit develops advanced, industry-leading ASICs for the hyperscale data center, enterprise, and AI infrastructure markets. Our products — including multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers — are critical enablers for efficient, high-bandwidth data transmission across fiber optical networks and electrical interconnects at 100G+ per lane.The ODSP team operates at the leading edge of semiconductor technology, developing chips in TSMC advanced process nodes. We are a global, multi-site engineering organization spanning Santa Clara, Ottawa, Pavia, Irvine, Vietnam, and Argentina — and we are looking for a senior staff DFT engineer in Santa Clara on our next-generation ODSP program, to help set up the methodology and flow on our flagship products.
What You Can Expect
- Define DFT architecture and implementation for a block within the chip, including hierarchical DFT, test modes and clocking.
- Plan, partition and integrate IP-level DFT (SerDes, PLL, memories, third-party IP).
- Drive ATPG coverage, test-time and pattern-count targets; optimize compression and power during test.
- Lead DFT sign-off: DRC, simulation, timing, equivalence, and handoff to PD/ATE.
- Debug silicon: failure isolation, diagnosis, yield learning with Product/Test engineering.
- Mentor junior engineers; review their work; coordinate with design, verification, PD, and test.
- Improve methodology and automation.
What We're Looking For
- BS in EE/CE with 8+ years or MS in EE/CE with 5+ years of DFT experience on complex SoCs, with multiple tape-outs and silicon bring-ups
- Deep expertise in scan, compression, ATPG fault models, MBIST/repair, JTAG, and at-speed test.
- Strong DFT timing/STA knowledge; experience with advanced nodes (7nm and below preferred).
- Proven independent problem solving and mentoring.
- Experience with high-speed SerDes/DSP products is a plus.
Expected Base Pay Range (USD)
134,390 - 201,300, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
#LI-TT1Skills Required
- BS in Electrical Engineering or Computer Engineering with 8 or more years of DFT experience on complex SoCs
- MS in Electrical Engineering or Computer Engineering with 5 or more years of DFT experience on complex SoCs
- Experience with multiple tape-outs and silicon bring-ups
- Expertise in scan, compression, ATPG fault models, MBIST and repair, JTAG, and at-speed test
- Strong DFT timing and static timing analysis knowledge
- Independent problem-solving ability and mentoring experience
- Experience with advanced process nodes, preferably 7nm and below
- Experience with high-speed SerDes or DSP products
Marvell Technology Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Marvell Technology and has not been reviewed or approved by Marvell Technology.
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Equity Value & Accessibility — Equity appears to be a meaningful part of total rewards through RSUs and an ESPP with a 15% discount and lookback, which can materially raise overall compensation. Stock upside is positioned as a key differentiator when company performance is strong.
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Parental & Family Support — Paid parental/bonding leave is described as substantial, with additional disability leave for birthing parents and a flexible return-to-work program. Family-care leave, generous bereavement provisions, and family-building support (e.g., adoption/surrogacy reimbursement) further strengthen the package.
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Healthcare Strength — Medical coverage is presented as broad with multiple plan options and preventive care covered at 100% in-network, alongside dental, vision, and structured mental-health support. Additional programs like telehealth and specialized care partners add depth to the health offering.
Marvell Technology Insights
What We Do
Marvell specializes in semiconductor solutions that power a wide range of industries, from data centers and 5G networks to AI, automotive, and storage applications. Our cutting-edge products are designed to meet the constantly evolving demands of a connected world, enabling faster, more efficient and more secure data processing and communication. With a focus on excellence and a commitment to advancing technology, we develop solutions that drive progress and transform industries.
Why Work With Us
Life at Marvell means being a part of new innovation and enduring technology; but it's also much more. Our diverse community is strengthened through cultural events, corporate gatherings and team-building activities, fostering collaboration and making work enjoyable. At Marvell, it's not just a job; it's an enriching, community-driven experience.
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