Sr Principal Design Engineer

Reposted 5 Days Ago
Be an Early Applicant
2 Locations
In-Office
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Lead DFT ownership across projects: define test architecture, implement RTL DFT changes, perform scan insertion/LEC/CLP checks, develop test-mode timing constraints, run ATPG and timing simulations, implement/verify boundary-scan, ACJTAG, IEEE1500 and IEEE1687 (iJTAG) ICL/PDL, support post-silicon bring-up, and interact with customers and pre-sales.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Experience: 10- 15 years

Location - Bangalore/Pune/

Responsibilities:

· Complete DFT ownership of projects including:

  • Test architecture definition.

  • Identifying and implementing RTL changes for DFT.

  • Performing scan insertion, LEC checks, low power CLP checks.

  • Developing timing constraints for test mode timing closure.

  • Scan and ATPG for different fault models.

  • Boundary scan, ACJTAG, IEEE 1500 implementation and verification.

  • IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests.

  • Running zero delay and timing simulations and debugging on all the above aspects.

  • Supporting post silicon bring up.

  • Interacting with customers on DFT aspects and support Marketing & Pre-Sales team.

  • Experience working on very high speed and low power designs.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • 10-15 years experience
  • Complete DFT ownership of projects
  • Test architecture definition
  • Identify and implement RTL changes for DFT
  • Perform scan insertion, LEC checks, low power CLP checks
  • Develop timing constraints for test mode timing closure
  • Scan and ATPG for different fault models
  • Boundary scan, ACJTAG, IEEE 1500 implementation and verification
  • IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests
  • Run zero delay and timing simulations and debug DFT/timing issues
  • Support post-silicon bring up
  • Interact with customers and support Marketing & Pre-Sales on DFT aspects
  • Experience with very high speed and low power designs

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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