Intel's HIPD team is looking for an experienced senior Logic design engineer to join the rapidly growing UCIE PHY IP for Intel's flagship datacenter/server designs.
Responsibilities will include but not limited to:
- Develops the logic design, register transfer level (RTL) coding, and simulation for IP block.
- Participates in the definition of architecture and microarchitecture features of the block being designed.
- Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
- Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
- Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Behavior skills we are looking for:
- Excellent written and oral presentation skills, and willing to work across multiple organizations and geographies.
- Effective team player with continuous learning mindset.
- Strong analytical and problem-solving skills.
- Be willing to balance multiple tasks.
- Ramp quickly on new and complex IPs in a dynamic environment is critical.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a Bachelor's degree in Electrical or Computer Engineering or a related field and 4+ years' experience OR a Master's degree in Electrical or Computer Engineering or a related field and 2+ years' experience OR a PhD in Electrical or Computer Engineering or a related field and 1+ years' experience.
Relevant Work Experience must be in:
- RTL/Logic design using System Verilog Language
- Experience with Design of Data path, Power-management flow, Arbitration logic, Clock Domain Crossing, State Machines, UPF
- Experience with Front End design tools for Lint, Synthesis.
- Experience with hardware simulation tools and methodologies (VCS/Verdi).
- Familiarity with IP environment and configuration management tools.
Preferred Qualifications:
- UCIE PHY Design and Mixed-Signal Environment.
- Cross Domain Crossing, Voltage Domain Crossings,
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:US, Arizona, Phoenix, US, Oregon, HillsboroPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor's in Electrical/Computer Engineering or related field + 4+ years OR Master's +2+ years OR PhD +1+ years experience
- RTL/Logic design using SystemVerilog
- Datapath design experience
- Power-management flow experience (UPF)
- Arbitration logic design experience
- Clock Domain Crossing (CDC) design experience
- State machine design experience
- Experience with front-end design tools for lint and synthesis
- Experience with hardware simulation tools and methodologies (VCS/Verdi)
- Familiarity with IP environment and configuration management tools
- UCIE PHY design experience
- Mixed-signal environment experience
- Voltage domain crossings / cross-domain crossing experience
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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