SoC Verification Engineer

Job Details:

Job Description: About the TeamPosition OverviewKey Responsibilities

• Create and update UVM-based test bench generation and test case creation
• Define and develop scalable and reusable block, subsystem, and SoC verification plans
• Create test benches and verification environments that align with microarchitecture specifications
• Execute verification plans, including emulation and system simulation models, to ensure design functionality and uncover bugs
• Debug and root cause issues in presilicon environments, implementing corrective measures to address failures
• Collaborate with architects, RTL developers, postsilicon teams, and physical design teams to improve verification of complex architectural features
• Document and maintain test plans, driving technical reviews with design and architecture teams
• Integrate security coverage activities within test plans, including regression and debug tests
• Maintain and improve existing functional verification infrastructure and methodologies
• Absorb learnings from postsilicon development and incorporate feedback into improved verification strategies

To Be Successful, You Should Demonstrate the Following

• Ability to work collaboratively across interdisciplinary teams
• Strong communication skills with the ability to work across interdisciplinary teams
• Passion for tackling complex problems and delivering innovative solutions

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 4+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning
  OR
• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 3+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning

• AMBA protocols such as CHI, AXI, AHB, and APB with industry-standard VIP from various EDA vendors
• Creation and updating of UVM-based test benches and test case creation

• Experience with postsilicon validation and incorporating feedback into presilicon test plans
• Familiarity with emulation models and system simulation tools for performance analysis

          

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, Texas, Austin

Additional Locations:US, California, Santa Clara, US, Oregon, Hillsboro

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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