SoC Design Verification Engineer

This role is for one of the Weekday's clients

Min Experience: 2+ years

Location: Bengaluru

JobType: full-time

We are looking for a SoC Design Verification Engineer to join our verification team and contribute to the validation of complex System-on-Chip (SoC) designs. In this role, you will work closely with Design Verification, RTL Design, Physical Design, DFT, and other cross-functional teams to develop and maintain robust top-level verification environments, debug complex issues, and ensure high-quality silicon delivery.

The ideal candidate should have hands-on experience with SystemVerilog/UVM, SoC verification methodologies, AMBA protocols, and debugging complex hardware interactions. Exposure to AI-assisted verification workflows is an added advantage.

• Develop, integrate, and maintain top-level SoC verification environments across multiple build configurations, including RTL, Gate-Level Simulation (GLS), netlist, and power-aware verification.
• Collaborate with Block Verification, RTL Design, Physical Design, and DFT teams to prepare verification collateral and build complete SoC verification environments.
• Debug failures from C-based and SystemVerilog/UVM-based test cases and perform root cause analysis.
• Track defects, coordinate with design teams for fixes, and validate resolutions through regression testing.
• Debug bus protocol transactions and port-level functional issues across complex SoC subsystems.
• Understand SoC boot flow and support verification of boot-related functionality.
• Build, maintain, and enhance UVM-based verification testbenches and reusable verification components.
• Execute functional verification using constrained-random methodologies and monitor functional coverage.
• Analyze simulation waveforms using industry-standard debugging tools to identify and resolve design or verification issues.
• Contribute to automation initiatives and explore AI-assisted workflows to improve verification productivity and debugging efficiency.

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
• Experience in SoC Design Verification using SystemVerilog and UVM.
• Good understanding of UVM testbench architecture and verification methodologies.
• Hands-on experience with AMBA protocols including AHB, AXI3, AXI4, APB, ACE-Lite, ACP, and GPIO interfaces.
• Knowledge of SoC boot flow and top-level integration verification.
• Experience debugging simulation failures and analyzing waveform data.
• Familiarity with simulation tools and verification debug environments.
• Working knowledge of Perl and/or Python scripting for verification automation.
• Strong analytical, debugging, and problem-solving skills.
• Excellent communication and collaboration abilities.

• Experience with Gate-Level Simulation (GLS), power-aware verification, and netlist verification.
• Exposure to AI-assisted verification workflows or AI-powered debugging tools.
• Familiarity with Cadence or Synopsys AI-enabled verification solutions.
• Knowledge of Agentic AI applications in verification and design automation.

• SoC Design Verification
• SystemVerilog
• UVM
• AMBA Protocols (AXI, AHB, APB)
• SoC Boot Flow
• UVM Testbench Development
• Simulation & Waveform Debugging
• Perl / Python Scripting

• Gate-Level Simulation (GLS)
• Power-Aware Verification
• AI-Assisted Verification
• Cadence / Synopsys Verification Tools
• Agentic AI
• Top-Level SoC Integration
• Functional Coverage
• Verification Automation