Sr. SoC Design Verification Engineer

Posted 3 Days Ago
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Bengaluru, Bengaluru Urban, Karnataka
In-Office
Senior level
Artificial Intelligence • Internet of Things • Machine Learning • Semiconductor
The Role
Responsible for verifying Design for Debug architecture, creating test cases and test benches using UVM. Coordinate cross-functional efforts for full coverage verification.
Summary Generated by Built In
Job Details:

Job Description:

As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification. Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan. Using system full application to verify performance and identify short falls.

Responsibility

  • Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification.
  • Create testcase and testbench with UVM methodology
  • Fullchip/system functional verification, by defining verification strategies/methodology​​ and test plan to enable effective verification
  • Coordinate/interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan
  • Experience on Emulation will be an add on.

Qualifications:
  • 10+ years of experience with complex ASIC designs and/or verification
  • Familiar with System Verilog language
  • Experience on UVM verification methodology, and formal verification method
  • Working knowledge of scripting in Linux/ Unix environments as well as proficiency in Perl and or Python is desirable.
  • Experience with Design for Debug (JTAG, High speed USB, PCIe based debug, Visualization of Internal Signal) architecture and design verification of same.
  • Experience with ARM and RISC Debug Architectures is desired with focus on design verification.
  • Any prior working experience on UltraSoC/ Tessent Embedded Analytics Debug Architecture will be a plus but not must for this position.
  • Strong communication skills and the ability to work with a team spread across different geography sites
  • Flexible in dynamic environment

Job Type: Regular

Shift:Shift 1 (India)

Primary Location:Bengaluru, Karnataka, India

Additional Locations:

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Top Skills

Jtag
Linux
Pcie
Perl
Python
System Verilog
Unix
Uvm
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The Company
HQ: San Jose, California
1,612 Employees
Year Founded: 1983

What We Do

Altera: Accelerating Innovators
Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.

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