SOC Design Verification Engineer

Job Details:

Job Description: 

• Intel is seeking a Design Verification Engineer for the Hard IP Division. In this technical role, you will define end-to-end verification strategy and execution for multiple Testchips from planning through signoff.
• You will partner closely with architecture, design, structural design, and IP teams to make early technical calls, unblock cross-team issues, and drive predictable high-quality delivery.
• This role requires deep DV expertise, strong protocol and memory subsystem knowledge, and enough breadth in RTL, physical design to contribute across traditional discipline boundaries.
• AI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected.
   

Responsibilities
- Define verification strategy, technical standards, and execution model for critical blocks and ensure on-time quality test collateral delivery to enable post-si team.
- Lead development of reusable environments, tools, and targeted testplans, including complex testbenches, checkers, VIPs, and behavioural models
- Collaborate closely with architecture, design, SD, Post-SI and methodology teams from specification through bring up; contribute across role boundaries when needed to unblock execution and maintain delivery quality
- Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs , Coverage closure, and GLS signoff
- Drive convergence of simulation and formal verification into unified bug hunting and coverage closure strategies; evaluate and adopt emerging methodologies including AI-driven verification flows
- Mentor and develop junior verification engineers; establish verification best practices and raise team-level execution quality.

Qualifications:

Minimum Qualifications
- BS/MS in Electrical Engineering, Computer Science, or related field, with 5+ years of relevant experience in design verification; extensive background in subsystem and SoC-level verification.
- Demonstrated experience in verification of global functions including debug, trace, clock and power management.
- Strong background in simulation and formal verification methodologies including UVM, SVA, ABV, and co-simulation; proficiency in low-power verification techniques, HDL/verification languages, and industry-standard EDA tools
- Advanced hands-on coding proficiency across SystemVerilog/UVM, C/C++, Python, and build systems; comfort using AI-assisted development tools as part of everyday workflow; track record of developing and delivering highly configurable and reusable verification collateral
- Working familiarity with RTL, physical design constraints, and tool flows; enough to read, review, and contribute outside core DV responsibilities
- Excellent communication and organizational skills with a track record of delivering high-quality silicon on schedule and establishing technical standards; able to adapt as tools, methodologies, and role definitions evolve.

          

Job Type:Experienced Hire

Shift:Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.