Silicon Front End CAD Verification Engineer

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About this opportunity:
Silicon Front-End CAD DV Engineer - Dual-Vendor Flows, Methodology & AI
Austin, Texas. This is not a remote work opportunity
Shape how Ericsson's ASICs and FPGAs are verified, from IP testbench to SoC regression. Combine deep SystemVerilog and UVM expertise with software engineering and practical AI to build faster, more reliable verification flows across silicon programs.
Work on ASIC and FPGA programs for Ericsson's 5G and 6G portfolio at advanced nodes, including Intel 18A and TSMC 3/2nm. Drive measurable gains in verification quality, coverage closure, and regression turnaround through reusable testbench architecture, qualified DV flows, and AI-driven automation.
Ericsson Silicon develops ASICs and FPGAs for telecommunications infrastructure. We are seeking a hands-on engineer to advance our front-end verification methodology, DV flows, and infrastructure-not simply support existing tools.
You will join a global methodology team spanning Austin, Stockholm, Lund, and India, working across verification methodology, EDA flow support, and OneRun, our front-end flow orchestration platform. Partner with IP and SoC verification teams, design and back-end methodology owners, and EDA vendors. Own qualified engineering solutions in your area; partner with the Silicon CAD Technical Program Manager on delivery and adoption. Project verification leads retain signoff approval.
What you will do• Architect scalable DV environments: Build layered, reusable SystemVerilog/UVM testbenches with clean separation, automated regression, and clear documentation. An early deliverable is a maintainable testbench for our register generation tool.• Develop high-quality VIP: Create efficient, reusable UVM verification IP with strong protocol checking, coverage, and low simulation overhead, independent of any single vendor's VIP library.• Advance verification methodology: Develop IP-to-SoC methodology across constrained-random and directed simulation, assertions, formal, and coverage closure. Keep environments portable across Cadence and Synopsys simulation and formal tools.• Apply AI to DV engineering: Use and improve AI tools such as ChipAgents and Kiro for testbench creation, spec-driven development, debug, and regression triage. Validate benefits against reproducible baselines; retain engineering review.• Deliver production-ready capabilities: Automate regression and release qualification in Jenkins CI and OneRun. Run representative pilots on real designs and support controlled rollout without disrupting active tapeout schedules.• Multiply technical impact: Resolve complex flow and tool issues, influence EDA vendor improvements, and mentor engineers through design reviews, documentation, and shared ownership.
Join our Team
What you will bring• 5+ years in ASIC/FPGA design verification or DV methodology, with evidence of production deployment and successful tapeout contributions.• Deep hands-on expertise in SystemVerilog and UVM testbench architecture at IP, subsystem, and SoC level, including constrained-random verification, SVA, and functional and code coverage closure.• Strong experience with Cadence Xcelium and/or Synopsys VCS, and formal or lint/CDC tools. Specialist depth in one domain is valued; expertise in every domain is not required.• Strong Python and scripting skills, with experience building maintainable automation using Linux, version control, code review, CI, automated tests, and controlled releases.• Demonstrated ability to turn difficult verification problems into reusable solutions across projects, explain technical trade-offs, and collaborate effectively in distributed teams.• A bachelor's or master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field-or equivalent practical experience.
Critical Exposure:
Practical application of AI/ML or LLM-based tools to testbench generation, coverage prediction, or failure triage; register-model development (UVM RAL, SystemRDL, IP-XACT); migrating verification environments between EDA vendors; or measurable improvements in coverage closure time and regression cost.
Own the engineering behind the verification flow-not just a step within it. Influence methodology, work directly with IP and SoC teams and EDA vendors, and turn new DV and AI ideas into production capabilities. Your impact will be measured in higher silicon quality, faster coverage closure, and verification environments that engineers trust across programs.
What happens once you apply?
Click Here to find all you need to know about what our typical hiring process looks like.
Ericsson uses a merit-based hiring approach that values people with different experiences, perspectives and skillsets. We truly believe this approach drives innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity employer, learn more.
If you need assistance or to request an accommodation due to a disability, please contact Ericsson at [email protected].
DISCLAIMER: The above statements are intended to describe the general nature and level of work being performed by employees in this position. They are not an exhaustive list of all responsibilities, duties and skills required for this position, and you may be required to perform additional job tasks as assigned.
Primary country and city: USA || Austin, Texas
Job details: Developer
Primary Recruiter: Jim Everett
Compensation and Benefits at Ericsson
At Ericsson, we know that our people are the key to our success. We offer a competitive package to help with your individual needs and goals.
Your Pay
The salary range for this position is dependent on various factors including, but not limited to, location, and the candidate's combination of job-related knowledge, qualifications, skills, education, training, and experience
Short-Term Variable Compensation Plan: Your pay also includes the opportunity for an annual bonus. Actual bonus payouts are based on performance of the business against the unit's objectives, individual performance, and the individual bonus target. Certain eligibility and pro-ration rules apply.
Your Health
Ericsson offers excellent health benefits including the choice of three medical plan options and a dental plan option that allow an employee to select the level of coverage that suits their needs. Employees will receive company credits in an amount equal to the cost that Ericsson pays toward the cost of their medical and dental premiums for themselves and eligible covered dependents.
Your Financial Security
We invest in both your short and long-term financial wellbeing. The Ericsson US 401(k) Plan offers an automatic 3% company contribution and Ericsson match $1 for every $1 you put into the 401(k) Plan on the first 3% of your eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay. When you contribute at least 5% of eligible pay, you are receiving Ericsson's full matching contributions of 4%. Matching and company automatic contributions stop when your total eligible pay for the year reaches the IRS limits. Employees will also receive company credits in an amount equal to the cost of basic life insurance and basic accidental death and dismemberment coverage, as well as short-term and long-term disability coverage. Employees also have the option to participate in Ericsson's Stock Purchase Plan.
Your Time
Your work-life balance is important to us. New employees are provided a minimum of 15 days of accrued vacation, up to 3 personal days per year, 11 annual holidays, 8 hours of volunteer time, and 80 hours of sick time annually. Please note paid time off is pro-rated based on the employee's start date. Furthermore, Ericsson provides up to 16 weeks of paid maternity leave and 6 weeks of parental or adoption leave at 100% of pay.
Additional Benefits
Ericsson offers many other company-paid benefits such as financial wellness programs, educational assistance, matching gifts, and recognition programs.