Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Position: Senior STA Engineer
Experience: 4–8 years
Location: Ahmedabad
Employment Type: Full-time
We are looking for a Senior STA Engineer with strong expertise in Static Timing Analysis, timing signoff, and timing closure for complex ASIC/SoC designs. The candidate will own timing analysis activities across the design flow and work closely with RTL, Synthesis, Physical Design, and Signoff teams to resolve complex timing issues.
Key Responsibilities- Own STA and timing signoff activities from synthesis through physical design and tape-out.
- Perform MCMM/MMMC timing analysis across all functional and test modes.
- Analyze and debug setup, hold, recovery, removal, min/max, and clock-related violations.
- Develop, review, and validate SDC constraints, including clocks, generated clocks, I/O delays, false paths, multicycle paths, and timing exceptions.
- Perform detailed clock tree and clock timing analysis, including skew, latency, uncertainty, jitter, and clock reconvergence.
- Drive timing closure in collaboration with RTL, synthesis, physical design, and ECO teams.
- Analyze critical timing paths and recommend design, synthesis, placement, routing, or ECO solutions.
- Perform timing analysis considering OCV/AOCV/POCV, derates, SI/crosstalk, and process-voltage-temperature variations.
- Review timing constraints and methodology to ensure signoff-quality timing analysis.
- Support timing ECOs and evaluate their impact across multiple corners and modes.
- Develop and maintain Tcl/Python automation for STA analysis, report generation, and flow optimization.
- Debug complex timing issues and provide technical guidance to junior STA engineers.
- Participate in methodology development, flow improvements, and timing signoff reviews.
- Coordinate with cross-functional teams to ensure project milestones and tape-out schedules are achieved.
- Strong expertise in Static Timing Analysis and timing closure.
- Hands-on experience with Synopsys PrimeTime, Cadence Tempus, or equivalent STA tools.
- Excellent knowledge of SDC constraints and timing exceptions.
- Strong understanding of ASIC/SoC design, synthesis, physical design, and signoff flows.
- Expertise in MCMM/MMMC analysis.
- Good understanding of OCV/AOCV/POCV, CPPR, SI/crosstalk, derating, and variation-aware timing.
- Strong knowledge of clock-domain timing, clock uncertainty, skew, latency, and clock reconvergence.
- Proficiency in Tcl scripting; Python/Perl scripting is an advantage.
- Strong debugging, analytical, and problem-solving skills.
- Ability to independently own STA for a block or full-chip design.
- Ability to identify root causes of complex timing violations and drive them to closure.
- Ability to interact effectively with design, RTL, synthesis, PD, CTS, and signoff teams.
- Experience mentoring junior engineers and reviewing their STA work.
- Strong ownership, communication, and project-management skills.
- Ability to work in a fast-paced semiconductor environment and deliver against tight tape-out schedules.
B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, or a related discipline.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Skills Required
- 4-8 years of experience in static timing analysis and timing closure
- Strong expertise in Static Timing Analysis and timing closure
- Hands-on experience with Synopsys PrimeTime, Cadence Tempus, or equivalent STA tools
- Excellent knowledge of SDC constraints and timing exceptions
- Strong understanding of ASIC/SoC design, synthesis, physical design, and signoff flows
- Expertise in MCMM/MMMC analysis
- Understanding of OCV, AOCV, POCV, CPPR, SI/crosstalk, derating, and variation-aware timing
- Knowledge of clock-domain timing, clock uncertainty, skew, latency, and clock reconvergence
- Proficiency in Tcl scripting
- Python or Perl scripting experience
- B.E., B.Tech, M.E., or M.Tech in Electronics, Electrical Engineering, VLSI, or a related discipline
- Ability to independently own STA for a block or full-chip design
- Experience mentoring junior engineers and reviewing STA work
Astera Labs Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.
-
Healthcare Strength — Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
-
Leave & Time Off Breadth — Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
-
Equity Value & Accessibility — Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.
Astera Labs Insights
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
