- As an SOC Timing engineer candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing.
- Candidate will be involved in static timing analysis, providing/deriving interface timing constraints to partitions and doing final timing signoff.
- Candidate will also work closely with design and architecture team for timing convergence analysis and will also work with physical design team for timing closure.
Proficient in physical design industry standard EDA tools such as Primetime/PTPX, Timing Constraints development and TCL, Python.
Good knowledge of physical design and PNR flow
Should have experience in timing signoff in 10nm or lower technology
BE/MS/Phd in Electronics/Electrical Engineering with 7+ Years’ experience timing closure and signoff.
Candidate should be strong in communication, problem solving and analytical skill
Top Skills
What We Do
Altera: Accelerating Innovators
Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.
