As a Sr. SoC Design Verification Engineer, you will be an owner of one or more architectural functional block to perform all verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification. Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan. Using system full application to verify i/o interface performance and identify short falls.
Responsibility
Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification.
Create testcase and testbench with UVM methodology
Fullchip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verification
Coordinate/interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan
Experience on Emulation will be an add on.
6+ years of experience with complex ASIC designs and/or verification
Familiar with System Verilog language
Experience on UVM verification methodology, and formal verification method
Experience with CPU architecture and any standard I/O interfaces, such as, Ethernet, PCIe, USB, DDR or HBM will be a plus.
Strong communication skills and the ability to work with a team spread across different geography sites
Flexible in dynamic environment
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