Senior Principal Design Engineer

Posted 8 Days Ago
Be an Early Applicant
2 Locations
In-Office
Senior level
Automotive • Internet of Things • Mobile • Semiconductor • Industrial
The Role
Lead SoC microarchitecture and RTL integration covering clocking, reset, interconnects, power, security, and functional safety. Own RTL signoffs (LINT/CDC/RDC), handoff checks, verification smokes, synthesis, requirements traceability (ISO26262/CMMi), IP integration reviews, BE report reviews, technical documentation, methodology adoption, and mentor engineering teams.
Summary Generated by Built In

The candidate shall be responsible for:
1. SoC u-Architecture for Clocking, Reset, Core & Interconnects, Power Management, Debug & Trace, Functional Safety, Security, IP/Subsystems integration etc.

2. SoC RTL Integration using state-of-the-art tools, flows & methodologies

3. LINT/CDC/RDC signoffs for the highest design quality

4. Handoff checks including Verification smokesuite and express Synthesis

5. Continuous learning using 3X5 Why based Root cause analysis, DFMEA, Lessons Learned for the product family

6. Requirements management and traceability including IS026262 / CMMi and other compliance requirements, working closely with System Architects, Applications, Design & Verification teams, Product & Test engineering, PMO and support functions

7. Overseeing technical documentation in close collaboration with information development team

8. Conducting IP Integration reviews, BE reports reviews for concurrent engineering

9. Driving key SoC design methodologies in close collaboration with global cross functional functional teams, Design Enablement etc.

10. Mentoring other engineers based on deep core competence and expertise

Soft skills expected:

1. Excellent collaboration skills and team work

2. Excellent verbal & written communication skills

3. Excellent presentation skills

4. Passion and can-do attitude

More information about NXP in India...

#LI-9415

Skills Required

  • SoC microarchitecture expertise (clocking, reset, core, interconnects, power management, debug/trace, security, functional safety)
  • SoC RTL integration using modern tools, flows and methodologies
  • LINT, CDC and RDC signoff experience
  • Handoff checks including verification smokesuite and express synthesis
  • Root cause analysis (3X5 Why), DFMEA and lessons-learned process experience
  • Requirements management and traceability, familiarity with ISO26262 and CMMi compliance
  • Experience overseeing technical documentation and coordinating with information development teams
  • Conducting IP integration reviews and back-end (BE) reports reviews
  • Driving SoC design methodologies and collaborating with global cross-functional teams
  • Mentoring and developing other engineers based on deep technical competence
  • Excellent collaboration, verbal and written communication, and presentation skills
  • Passion and a strong can-do attitude
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The Company
HQ: Eindhoven
21,993 Employees
Year Founded: 2006

What We Do

NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer and more sustainable world through innovation. As a world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 34,500 employees in more than 30 countries and posted revenue of $13.21 billion in 2022. Find out more at www.nxp.com. Privacy Policy: https://www.nxp.com/company/about-nxp/privacy-policy-for-social-media-pages:PRIVACY-POLICY-SOCIAL-MEDIA

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