We are looking for an experienced C++ software engineer to join the Protium Software Development Team to develop and enhance the FPGA-Based Prototyping product which is used by leading CPU/GPU/HyperScaler companies for pre-Silicon software validation of their SOC’s.
You will develop new algorithms and optimizations for QoR (Quality of Results) and performance for the Protium Timing flow working with a small team of engineers to develop our next generation FPGA based verification platform.
Responsibilities:
- Enhance and support Timing Engine to add new features and extend existing features
- Enhance and support Timing Flow to improve P&R compile time
- The role involves designing, tuning, and innovating timing graph algorithms and flow operating on multi‑billion‑node timing graphs
- Write Specifications and Unit Tests for your code
Position Requirements/Qualifications:
- BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
- Experience in EDA software development.
- Strong background in SDC constraints and Timing Analysis
- Excellent programming skills in C/C++
- Strong knowledge of Tcl is preferred
- Experience in multi-threaded/ concurrent programming are pluses.
- Prior experience with Emulation or FPGA software development is an added plus.
The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.Skills Required
- BS with 10 years of experience or MS with 7 years or PhD with 5 years
- Experience in EDA software development
- Strong background in SDC constraints and Timing Analysis
- Excellent programming skills in C/C++
- Strong knowledge of Tcl
- Experience in multi-threaded/concurrent programming
- Prior experience with Emulation or FPGA software development
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
