Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com.
As an Astera Labs Senior Physical Design Engineer (STA) you will play a crucial role in overseeing the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. To accomplish that, you will work closely with designers, verification engineering, and engineering operations. This role is fully on-site and in-person.
Basic Qualifications:
- Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred.
- ≥3 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
- Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
Required Experience:
- Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block and full-chip level.
- Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
- Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.
- Experience with Cadence and/or Synopsys physical design tools/flows.
- Familiarity and working knowledge of System Verilog/Verilog.
- Experience with DFT tools and techniques.
- Experience in working with IP vendors for both RTL and hard-macro blocks.
- Good scripting skills in tcl, python or Perl.
Preferred Experience:
- Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.
- Familiarity with DFT test coverage and debug.
- Familiarity with ECO methodologies and tools.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Top Skills
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center.
Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning.
The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
