Senior Mask Layout Design Engineer

Posted 17 Days Ago
Be an Early Applicant
2 Locations
In-Office
132K-236K Annually
Senior level
Artificial Intelligence • Computer Vision • Hardware • Robotics • Metaverse
The Role
Perform physical mask layout for mixed-signal circuits, including PLLs, high-speed I/O, general I/O, and ESD structures, using Cadence tools and advanced CMOS technologies. Collaborate with ASIC and mixed-signal engineers on floor planning, custom layout, top-level integration, and design verification. Run and debug DRC/LVS checks, customize verification decks, and support tape-outs using FinFET technologies.
Summary Generated by Built In

Are you interested in joining our Dynamic team? If yes, We are looking for a Senior Mask Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling high-speed mixed-signal circuit designs!


NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence.


What you'll be doing:

  • Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in innovative sub-micron CMOS technologies using Cadence tools
  • You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products and Job duties will include floor planning, custom layout and verifying against design rules and schematics.

What we need to see:

  • Hold a BSEE or equivalent experience. MSEE is a plus.
  • 8+ years of relevant mask design / layout experience
  • Tape-out experience with FinFET technology is required. Experience with TSMC N5/N4/N3 is preferred.
  • Experience with high-speed SerDes/RF layout design is helpful and Experience with top level integration would be excellent to have.
  • Deep understanding of analog circuit layout concepts in submicron CMOS technologies
  • Validated experience with Cadence custom circuit design tools - particularly virtuoso
  • Experience running and debugging DRC and LVS with verification tools such as ICV/Calibre
  • Ability to work optimally in a team, good interpersonal skills and positive energy.
  • Proficiency in scripting languages like perl, python, skill etc. is a plus
  • Knowledge of DRC and LVS checking flows, ability to customize DRC and LVS decks

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 132,000 USD - 207,000 USD for Level 4, and 148,000 USD - 235,750 USD for Level 5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until October 10, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Skills Required

  • Bachelor of Science in Electrical Engineering or equivalent experience
  • Master of Science in Electrical Engineering
  • 8 or more years of relevant mask design or layout experience
  • Tape-out experience with FinFET technology
  • Experience with TSMC N5, N4, or N3 technologies
  • Experience with high-speed SerDes or RF layout design
  • Experience with top-level integration
  • Deep understanding of analog circuit layout concepts in submicron CMOS technologies
  • Validated experience with Cadence custom circuit design tools, particularly Virtuoso
  • Experience running and debugging DRC and LVS with ICV or Calibre verification tools
  • Ability to work effectively in a team with strong interpersonal skills
  • Proficiency in Perl, Python, or SKILL scripting
  • Knowledge of DRC and LVS checking flows and ability to customize DRC and LVS decks

NVIDIA Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about NVIDIA and has not been reviewed or approved by NVIDIA.

  • Equity Value & Accessibility — Equity awards and a discounted ESPP are highlighted as core parts of total compensation, enabling employees to share in the company’s success. Stock-based compensation and the two-year lookback ESPP are consistently described as especially valuable.
  • Healthcare Strength — Health coverage is portrayed as robust, with comprehensive medical, dental, and vision options alongside mental health support and on-site care resources. Employer HSA contributions and wellness perks reinforce the depth of the offering.
  • Retirement Support — Retirement programs are depicted as strong, featuring a meaningful 401(k) match with Roth options and support for Mega Backdoor Roth contributions. These elements position long-term savings as a notable advantage of the total rewards package.

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The Company
HQ: Santa Clara, CA
21,960 Employees
Year Founded: 1993

What We Do

NVIDIA’s invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing — with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. Today, NVIDIA is increasingly known as “the AI computing company.”

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