Senior Engineer - Static Timing Analysis

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About this Opportunity
Join Ericsson's cutting-edge journey to shape the future of 5G networks! As a Static Timing Analysis Engineer, you'll work on pioneering digital ASIC designs vital to Ericsson's mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you're passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you.
At Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you'll find a supportive, innovative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom!
About the Role
We are hiring a Static Timing Analysis Engineer to own timing signoff on high-performance, low-power SoC designs at advanced process nodes. Your primary focus will be full-chip STA, constraint development, MMMC corner closure, and driving timing convergence across implementation teams - while also contributing to physical synthesis flows as well. You will be a critical partner to P&R, synthesis, and RTL teams from design kick-off through tape-out.
What you will do:
Full-Chip STA & Signoff• Own end-to-end STA signoff using Synopsys PrimeTime (PT / PT-SI) across all design modes and corners.• Perform timing checks; drive violations to closure with P&R and synthesis teams.• Execute MMMC (Multi-Mode Multi-Corner) analysis across full PVT space including OCV, AOCV, and POCV derating methodologies.• Lead timing signoff checklist definition, gate reviews, and tape-out timing closure certification.• Perform timing checks in Low Power Modes (UPF/CPF, Power domains etc)
Constraint Development & Management• Author, own, and maintain full-chip SDC constraints - clock definitions, generated clocks, I/O delays, and timing exceptions (false paths, multicycle paths).• Audit and validate constraints from RTL teams and third-party IP; resolve SDC inconsistencies between synthesis and post-layout STA.• Perform clock domain crossing (CDC) and reset domain crossing (RDC) timing analysis; collaborate with formal verification teams on structural CDC checks.• Develop and enforce constraint management methodology across hierarchical and flat design flows.
Timing Closure• Establish and track timing closure metrics (WNS, TNS, failing endpoint count) across design milestones; present status to project leadership.• Perform SI (Signal Integrity) - crosstalk-induced delay and glitch analysis using PT-SI; define and validate noise budgets.
Physical Synthesis • Support RTL synthesis runs using Design Compiler - review QoR results and provide timing-driven feedback to the synthesis team.• Assist in SDC constraint development and validation during synthesis, ensuring consistency with post-layout STA.• Review synthesis netlist quality - flagging timing bottlenecks, high-fanout nets, and problematic structures before P&R hand-off.• Contribute to physical-aware synthesis iterations by providing critical path and congestion context from STA perspective.• Participate in DFT-aware synthesis reviews - validate that scan insertion and BIST integration do not adversely impact timing budgets.
The skills you bring:
• B.Tech / M.Tech / M.S. in Electronics Engineering, VLSI Design, Computer Engineering with 10+ Years of experience in STA or timing closure roles.• Expert-level PrimeTime proficiency• Deep SDC constraint authoring and auditing skills• MMMC, OCV/AOCV/POCV timing methodologies• PT-SI / crosstalk and noise analysis experience• Working knowledge of synthesis (DC)• Proficiency in Tcl; Python scripting a strong plus• At least one tape-out on 7nm or below.
Nice to Have:
• Familiarity with P&R tools for timing-driven closure• Understanding of PTPX-based power and timing co-analysis• Exposure to formal CDC/RDC verification (SpyGlass, VC SpyGlass)• Knowledge of CTS (Clock Tree Synthesis) and its timing impact• Background in Liberty (.lib) characterization and NLDM/CCS models• Strong foundation in digital logic design, CMOS circuit fundamentals, and standard-cell library concepts.• Analytical mindset with proven ability to debug complex timing failures across large, multi-million gate designs.
EDA Tools & Environment
PrimeTime/PT-SI SpyGlass CDC Design Compiler Fusion Compiler Tcl/ Python.
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"All academic credentials must be from recognized and accredited institutions and are further subject to verification"
Why join Ericsson?At Ericsson, you'll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what's possible. To build solutions never seen before to some of the world's toughest problems. You'll be challenged, but you won't be alone. You'll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.
What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.
Primary country and city: India (IN) || Bangalore
Req ID: 786039