Senior Engineer - Power Estimation/Power Optimization

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

Job Description

The Power Estimation Engineer will be responsible for driving the development and implementation of power estimation methodologies and tools for our wireless SoC chips. This role involves collaboration with various teams to ensure accurate power estimation and optimization.

Responsibilities

• Lead the development and implementation of power estimation methodologies for wireless SoC chips.

• Collaborate with cross-functional teams including RTL design, verification, physical design, and software teams to integrate power estimation solutions.

• Develop and enhance testbenches for block-level and system-level power estimation.

• Conduct power analysis and optimization at various stages of the design flow.

• Provide detailed power estimation reports and documentation in accordance with company quality requirements.

• Manage cross-functional dependencies and support system-level power estimation and optimization efforts.

• Report on power estimation results and resolve action items generated from reviews.

Experience Level: 5+ years in Industry

Education Requirements: Bachelor or Master’s degree in Electrical or Computer Engineering

Qualifications:

• Strong understanding of power estimation concepts and low-power design techniques.

• Experience with power estimation tools and methodologies such as Voltus, PrimePower, and Joules

• Familiarity with digital circuit design and verification.

• Hands-on experience with FPGA designs and testing.

• Excellent collaboration and communication skills.

• Experience in full-chip development cycle

• Knowledge of scripting languages like Perl, Python, Tcl, shell

Benefits & Perks

You can look forward to the following benefits:

Equity Rewards (RSUs)

Employee Stock Purchase Plan (ESPP)

Insurance plans with Outpatient cover

National Pension Scheme (NPS)

Flexible work policy

Childcare support