Senior ASIC Timing Engineer

Come be a part of new process technology adoption by joining NVIDIA's Advanced Technology Group! Work as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are problem solver and highly motivated individual searching for a collaborative and exciting role, join us today. We encourage applicants with a history of proven success working in a multicultural and diverse environment.

 

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.

 

What you'll be doing:

• You will be responsible for all aspects of timing including, timing analysis and closure, timing environment, setting up constraints and defining the timing methodology for the next generation of designs. This includes working with place and route to understand and implement around their constraints.

• Finding the right tradeoffs and balance between frequency and power/area/congestions/yield/etc.

• Work on all aspects of DFT/Test timing such as timing constraints, timing analysis, timing convergence, and ECO implementation.

 

What we need to see:

• Hold a BS in Electrical or Computer Engineering or equivalent experience.

• 8+ years experience in Physical design/Timing.

• Experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.

• In-depth understanding of multiplexed scan logic and constraints.

• Expertise in physical design, optimization, and ECO implementation e.g. cell sizing, buffering, vt swap.

• Hands-on knowledge of industry standard Timing/STA EDA tools.

• Proficiency in programming and scripting languages, such as TCL and Python.

 

Ways to stand out from the crowd:

• Experience with DFT timing closure for various modes e.g. scan shift, scan capture, transition faults, BIST, etc.

• Knowledge of clocking and clock controls in DFT modes.

• Experience in methodology or flow development.

 

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're creative and autonomous, we want to hear from you.
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Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.Applications for this job will be accepted at least until August 15, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.