Senior ASIC Research Engineer – Front-end Digital Design

Posted Yesterday
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Arlington, VA, USA
In-Office
140K-170K Annually
Senior level
Edtech
The Role
Design and verify RTL models for CPUs, memories, and accelerators used in communications, signal processing, and security applications. Develop advanced ASIC prototypes, integrate third-party IP, use EDA tools for synthesis and timing, and collaborate with research sponsors and MOSIS 2.0. The role also involves digital design verification, performance modeling, FPGA workflows, agile hardware methodologies, and AI-assisted engineering in a research environment.
Summary Generated by Built In

USC’s Information Sciences Institute (ISI), a unit of the university’s Viterbi School of Engineering, is a world leader in the research and development of advanced information processing, computing, communications and artificial intelligence technologies. ISI’s 400 faculty, professional staff and graduate students carry out extraordinary information sciences research at three distinct locations - Arlington, VA; Marina Del Rey, CA; and Waltham, MA.


ISI’s Computational Systems & Technology Division has an opening in Arlington, VA for a Senior ASIC Research Engineer – Front-end Digital Design, to design advanced ASIC prototypes addressing problems of national importance. The Engineer will work with a cutting-edge team to design and verify register-transfer level (RTL) models of CPUs, memories, and accelerators for applications such as communications, signal processing, and security. The Engineer will have opportunities to collaborate with ISI’s MOSIS 2.0 service, integrate third-party IP cores, and gain experience working with top research sponsors such as DARPA, IARPA, and the CHIPS Act. The position provides a collaborative, flexible university setting with rich learning and growth opportunities. The Engineer will gain experience in a fast-moving research setting and work toward a better and more secure future.


The work will be based in ISI's Arlington, VA office.


Minimum Qualifications:
  • Ability to handle Controlled Unclassified Information (CUI). Per U.S. government regulations, eligibility to handle CUI requires U.S. Citizenship or Permanent Residency.
  • Degree in Computer Engineering, Electrical Engineering, or related field
  • Master’s degree with >5 years of experience
  • Demonstrated excellence creating digital designs with Verilog, System Verilog, or VHDL RTL
  • Solid understanding of computer architecture and microarchitecture
  • Demonstrated skills with EDA tools (logic synthesis, timing), scripting, revision control

Preferred Job Qualifications:
  • Familiarity with digital design verification
  • Familiarity with performance modeling
  • Familiarity with agile hardware design methodologies
  • Experience with AI-assisted workflows
  • Experience using FPGAs
  • Effective at verbal communication and giving clear explanations

The annual base salary range for this position is $140,000 to $170,000. When extending an offer of employment, the University of Southern California considers factors such as (but not limited to) the scope and responsibilities of the position, the candidate’s work experience, education/training, key skills, internal peer equity, federal, state, and local laws, contractual stipulations, grant funding, as well as external market and organizational considerations.


Why work at ISI:
  • Work on exciting and engaging projects that have real-life impact.
  • Small project team environment allows for involvement across entire project lifecycle.
  • A quality work-life balance.
  • Opportunities for free, top-tier university education for you and your children.
  • Great benefits - medical to matched retirement 

Minimum Education: Bachelors, combined experience/education as substitute for minimum education
Minimum Experience: 8 years
Minimum Skills: Experience with Linux. Excellent written and oral communication skills.
Preferred Education: Master's degree
Preferred Experience: 10 years
Preferred Skills: Proven leadership ability. Experience with artificial intelligence, very large-scale integration design, machine learning, deep learning (e.g., TensorFlow, PyTorch, HuggingFace), and Dockerization.

                                                  

USC is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability, or any other characteristic protected by law or USC policy. USC observes affirmative action obligations consistent with state and federal law. USC will consider for employment all qualified applicants with criminal records in a manner consistent with applicable laws and regulations, including the Los Angeles County Fair Chance Ordinance for employers and the Fair Chance Initiative for Hiring Ordinance, and with due consideration for patient and student safety. Please refer to the Background Screening Policy Appendix D for specific employment screen implications for the position for which you are applying. 

We provide reasonable accommodations to applicants and employees with disabilities. Applicants with questions about access or requiring a reasonable accommodation for any part of the application or hiring process should contact USC Human Resources by phone at (213) 821-8100, or by email at [email protected]. Inquiries will be treated as confidential to the extent permitted by law.

  • Notice of Non-discrimination
  • Employment Equity
  • Read USC’s Clery Act Annual Security Report
  • USC is a smoke-free environment
  • Digital Accessibility

                                                  

If you are a current USC employee, please apply to this  USC job posting in Workday by copying and pasting this link into your browser:

https://wd5.myworkday.com/usc/d/inst/1$9925/9925$155716.htmld

Skills Required

  • U.S. citizenship or permanent residency to handle Controlled Unclassified Information
  • Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related field
  • At least 8 years of professional experience
  • Demonstrated excellence creating digital designs with Verilog, SystemVerilog, or VHDL RTL
  • Solid understanding of computer architecture and microarchitecture
  • Experience with EDA tools for logic synthesis and timing
  • Experience with scripting and revision control
  • Experience with Linux
  • Excellent written and oral communication skills
  • Master’s degree with more than 5 years of experience
  • Familiarity with digital design verification
  • Familiarity with performance modeling
  • Familiarity with agile hardware design methodologies
  • Experience with AI-assisted workflows
  • Experience using FPGAs
  • Effective verbal communication and ability to give clear explanations
  • Master’s degree
  • At least 10 years of experience
  • Proven leadership ability
  • Experience with artificial intelligence, VLSI design, machine learning, or deep learning
  • Experience with TensorFlow, PyTorch, or Hugging Face
  • Experience with Dockerization
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