Senior Analog Layout Design Engineer

This role is for one of the Weekday's clients

Salary range: Rs 1500000 - Rs 3000000 (ie INR 15 - 30 LPA)

Min Experience: 4+ years

Location: Bengaluru
JobType: full-time

We are looking for a highly skilled Senior Analog Layout Design Engineer with 4–6 years of hands-on experience in analog and mixed-signal IC layout design. The ideal candidate will possess strong expertise in developing high-quality transistor-level layouts while ensuring compliance with advanced semiconductor process technologies and design methodologies. You will work closely with circuit designers, verification engineers, and fabrication teams to deliver robust, manufacturable layouts that meet stringent performance, reliability, and yield requirements.

This role requires a detail-oriented engineer with excellent problem-solving skills and a deep understanding of physical layout implementation, verification, and optimization for high-performance analog circuits.

• Design and implement transistor-level layouts for analog and mixed-signal integrated circuits including amplifiers, voltage regulators, PLLs, ADCs, DACs, LDOs, bandgap references, and other custom analog blocks.
• Develop optimized layouts that meet electrical performance, area, matching, noise, and reliability requirements.
• Perform layout verification using Design Rule Check (DRC) and Layout Versus Schematic (LVS) to ensure design correctness and manufacturability.
• Collaborate closely with circuit designers throughout the layout cycle to resolve layout-dependent effects and improve overall circuit performance.
• Optimize layouts for parasitic reduction, matching accuracy, electromigration, IR drop, and process variations.
• Execute floorplanning and block-level integration while maintaining design quality and schedule commitments.
• Participate in design reviews and provide technical recommendations to improve layout methodologies and best practices.
• Support tape-out activities and work with cross-functional teams to resolve physical verification issues.
• Maintain layout documentation and adhere to company design standards and process guidelines.

• Strong hands-on experience in Analog Layout design for custom IC development.
• Excellent knowledge of DRC (Design Rule Check) and resolving design rule violations.
• Proficiency in LVS (Layout Versus Schematic) verification and debugging layout mismatches.
• Strong understanding of device matching techniques, common centroid layouts, shielding, guard rings, symmetry, and routing strategies.
• Knowledge of semiconductor fabrication processes and layout-dependent effects.
• Ability to interpret circuit schematics and translate them into optimized physical layouts.
• Strong analytical, debugging, and problem-solving abilities.
• Excellent communication and collaboration skills.

• Experience performing PEX (Parasitic Extraction) and analyzing extracted results.
• Hands-on experience with Cadence Virtuoso for custom layout development.
• Familiarity with Calibre for physical verification, DRC, LVS, and PEX flows.
• Exposure to FinFET or advanced process nodes is an added advantage.
• Knowledge of reliability checks including ERC, antenna checks, and electromigration analysis.

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Microelectronics, VLSI Design, or a related discipline.
• 4–6 years of professional experience in analog or mixed-signal layout design.
• Proven experience working on full custom layout development through successful tape-outs.
• Ability to work independently while effectively collaborating within multidisciplinary engineering teams.