RTL-to-GDS implementation, Senior Principal Solutions Engineer

Posted Yesterday
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Austin, TX, USA
In-Office
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Supports Cadence product adoption and customer RTL-to-GDSII implementation projects. Performs synthesis, place and route, clock tree synthesis, static timing analysis, low-power and multi-voltage implementation, timing debugging, tapeout support, and full-flow methodology development. Leads customer evaluations, competitive benchmarks, technical presentations, and implementation services across advanced technology nodes for complex CPU, GPU, DSP, wireless, and mobile designs.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The primary focus of Senior Principal Solutions Engineer is to support the adoption of Cadence Products to help Chip Designer Customers achieve superior performance for their Design PPA Goals. AE's are expected to possess Synthesis (logical and physical), Place and Route (primary focus) , STA / SDC skills and some experience supporting tapeouts. Experience with multivoltage design implementation and clock tree debugging is desirable. 

In addition, Solutions Engineers are expected to be able to articulate design methodologies involving Cadence tools and be 'elevator talk' proficient in the full Cadence tool portfolio. Development time will be spent gaining expertise in additional, or specialization tools, broadening focus from product emphasis to methodology, Full Flow Implementation Training, and learning to leverage success . Full Flow Services Projects involves owning block implementation, top level implementation and Signoff focused efforts. Job exposure will be on RTL to GDSII delivery of projects. There's an opportunity to get involved in competitive benchmarking on complex blocks including CPUs, GPUs and DSP cores. These projects involve implementation in multiple technology nodes on standard foundry solutions. If you are looking to gain experience in methodology, product delivery, and working on cutting edge technology, this is the right role for you.

Position Requirements: 

* 7+ years experience and a strong technical knowledge of company products. 

* Design experience should include ASIC design using industry-standard hardware description languages (Verilog) 

* Senior Level Applications Engineer position with Deep Cadence or Synopsys place and route tool knowledge (Physical Synthesis, PnR, CTS, Static Timing Analysis) experience and knowledge are required 

* Innovate with Low Power and Multi-Voltage Design Techniques working with leading edge Wireless and Mobile Customers 

* Senior level Design Engineer position supporting RTL-to-GDS implementation flows using Encounter Digitial Implementation Platform 

* Manage strategic customer evaluations/benchmarks on Cadence's front-end solutions to establish technology differentiation and assert Cadence competitive advantages. Multiplex several issues and set priorities and exploit new technologies are essential for success in the position 

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • 7+ years of experience
  • Strong technical knowledge of Cadence products
  • ASIC design experience using Verilog or other industry-standard hardware description languages
  • Cadence or Synopsys place-and-route tool experience
  • Physical synthesis, place and route, clock tree synthesis, and static timing analysis experience
  • Experience supporting RTL-to-GDS implementation flows using the Encounter Digital Implementation Platform
  • Low-power and multi-voltage design implementation experience
  • Experience supporting customer evaluations, benchmarks, and competitive technology assessments
  • Tapeout support experience
  • Clock tree debugging experience

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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