RTL Design Engineer

This role is for one of the Weekday's clients

Salary range: Rs 600000 - Rs 1400000 (ie INR 6-14 LPA)

Experience: 3+ yrs

Location: Bengaluru

Job Type: Full-Time

We are looking for a skilled RTL Design Engineer with strong expertise in digital design and SoC development. In this role, you will be responsible for designing, developing, and integrating high-quality RTL blocks while ensuring functionality, performance, power efficiency, and design quality. You will collaborate with cross-functional engineering teams throughout the ASIC development lifecycle, contributing to architecture definition, RTL implementation, verification, and successful SoC integration. This position is ideal for engineers who are passionate about digital design, hardware architecture, and delivering reliable semiconductor solutions.

• Design and develop RTL modules using Verilog, SystemVerilog, or VHDL based on functional and architectural specifications.
• Define block-level design documentation, including interface protocols, block diagrams, transaction flows, pipeline architecture, and functional specifications.
• Perform RTL implementation while ensuring design quality, scalability, and maintainability.
• Execute design quality checks, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and Unified Power Format (UPF) validation.
• Optimize RTL for performance, area, and power through efficient logic synthesis and low-power design techniques.
• Integrate IPs and subsystems into complex SoC environments while ensuring seamless functionality.
• Collaborate with verification teams to support unit-level testing, test planning, coverage analysis, and functional validation.
• Work with standard on-chip communication protocols such as AMBA, UART, I2C, SPI, I2S, Timers, and related peripheral interfaces.
• Participate in ASIC-level verification activities and support debugging of design and integration issues.
• Collaborate effectively with architecture, verification, physical design, and software teams across multiple locations to ensure successful project execution.
• Contribute to design reviews, technical discussions, and continuous improvement of RTL development methodologies.

• Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related technical discipline.
• Strong hands-on experience in RTL Design using Verilog, SystemVerilog, or VHDL.
• Solid understanding of digital logic design principles, RTL coding practices, and hardware architecture.
• Experience with Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and UPF methodologies.
• Good knowledge of logic synthesis, RTL optimization, and low-power design techniques.
• Experience integrating IPs and subsystems within complex SoC designs.
• Familiarity with unit-level verification methodologies, test planning, and coverage analysis.
• Strong understanding of industry-standard protocols such as AMBA, UART, I2C, SPI, I2S, and Timer IPs.
• Excellent analytical, debugging, and problem-solving skills with attention to design quality and performance.
• Strong communication and collaboration skills with the ability to work effectively in cross-functional and globally distributed engineering teams.