RTL Design Engineer

Reposted 11 Days Ago
Be an Early Applicant
Bengaluru, Bengaluru Urban, Karnataka, IND
In-Office
Senior level
Information Technology • Professional Services • Consulting
The Role
Design and implement IP/sub-system micro-architecture and RTL, create block-level timing constraints, integrate IP, perform basic verification in IP or FPGA, and work with synthesis, CDC, lint, and timing for ASIC/FPGA flows.
Summary Generated by Built In
Company Description

Client of FiniteHR, Startup

Job Description

Our Client SeviTech is looking for RTL Design Engineer

About our Client: http://sevitechsystems.com/

Job Designation: RTL Design Engineer.

Job Location: Bangalore

Job Type: Permanent 

 • You will be responsible for IP / sub-system level micro-architecture development and RTL coding.

• Prepare block/sub-system level timing constraints.

• Integrate IP/sub-system.

• Perform basic verification either in IP Verification environment or FPGA. 

 • B. Tech. or M. Tech. with 4 to 8 years of experience.

• Experience in Logic design / micro-architecture / RTL coding is a must.

• Expertise in Verilog is a must.

• Should have knowledge of AMBA protocols - AXI, AHB, APB.

• Experience in Synthesis / Understanding of timing concepts for ASIC or experience in Xilinx FPGA Design Implementation is required.

• Experience in design of DDR / USB / PCIe controller or such complex protocols is a plus.

• Hands on experience in Multi Clock designs, Asynchronous interface is a must.

• Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation etc. is required.

• Knowledge of low power concepts and experience is a plus. 

This is an Immediate Opportunity candidate with less than one month notice will be 

preferred.

Please ignore this mail if the above profile doesn’t match with your current Job Role.

Thank you for your Valuable Time

Hoping for a Prompt Response!!!

Best regards,

Eswar-Recruiter

FiniteHR Consulting Pvt Ltd.

Additional Information

All your information will be kept confidential according to EEO guidelines.

Skills Required

  • B.Tech or M.Tech with 4 to 8 years of experience
  • Experience in logic design, micro-architecture, and RTL coding
  • Expertise in Verilog
  • Knowledge of AMBA protocols (AXI, AHB, APB)
  • Experience in synthesis and understanding of timing concepts for ASIC or Xilinx FPGA implementation
  • Hands-on experience in multi-clock designs and asynchronous interfaces
  • Experience with ASIC development tools (lint, CDC, simulation)
  • Experience in design of DDR/USB/PCIe controllers or other complex protocols
  • Knowledge of low power design concepts
  • Availability with less than one month notice
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The Company

What We Do

FiniteHR is a Human Capital Management organization, has been in business since 2014 in Hyderabad, serving IT and non IT clients in Domestic and International markets. They are a team of dedicated professionals with expertise in recruiting professionals and specialized experts across North America, Asia, Middle East and Europe, acting as an ideal outsourcing partner for recruitment and staffing services.

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