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The Role
Drives RTL-to-GDS physical design convergence for high-performance semiconductor technologies. Responsibilities include floorplanning, synthesis, place-and-route, timing closure, power and clock distribution, congestion analysis, IR drop analysis, physical verification, ECOs, and sign-off. The engineer collaborates with CAD, methodology, and custom IP teams to optimize memory macros, standard cells, packaging, yield, and design productivity while developing advanced physical design workflows.
Summary Generated by Built In
Job Details:Job Description: The Role and Impact
As a Physical Design Engineer, you will play a critical role in driving the development of cutting-edge technologies at Intel. You will work hands-on to deliver high-performance physical designs, ensuring the successful integration of advanced semiconductor technologies. Your work will directly impact Intel's product innovation, addressing complex challenges in power, performance, and area optimization to shape the future of computing architectures. From synthesis to sign-off, your contributions will enable Intel to meet ambitious design goals and deliver transformative solutions to the market.
Business Group
This role is part of Intel's Corporate Technology Office (CTO), a dynamic group dedicated to advancing the company's technological leadership and innovation. The group focuses on developing foundational technologies, architectures, and methodologies that drive Intel's product roadmap and enable breakthrough computing solutions. Collaborating with cross-disciplinary teams, the CTO plays a pivotal role in delivering impactful designs that support Intel's broader mission of creating world-changing technology.
Key Responsibilities
- Drive RTL-to-GDS design convergence using advanced synthesis and place-and-route tools targeting performance, power, and area (PPA) goals.
- Deliver block-level physical design, including closure of backend flows, electrical requirements, and enhancing silicon yield.
- Collaborate with CAD and physical design methodology teams to adopt industry-leading tools and optimizations for custom designs.
- Execute physical implementation tasks such as floor planning, bus/pin placement, power/clock distribution, congestion analysis, timing closure, IR drop analysis, and physical verification.
- Debug timing, EM/IR, LVS, and DRC violations, and drive sign-off activities for high-quality silicon production.
- Work closely with custom IP teams to define and optimize memory macros and standard cell libraries to improve overall design efficiency.
- Develop and refine physical design methodologies to enhance workflow and productivity.Qualifications:Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field and 6+ years of hands-on physical design experience OR a Master's degree with 4+ years of relevant experience.
- Demonstrated experience in floor planning, timing constraints definition, synthesis, place-and-route, and achieving product KPIs.
- Proficiency in scripting languages such as Python, Perl, and TCL for design flow automation and debugging.
- Hands-on experience with debugging functional equivalence verification (FEV) and RV reports, including planning and implementing engineering change orders (ECOs).
- Strong understanding of chiplet integration and advanced packaging techniques.
- Experience leveraging AI tools to set up workflows, streamline debugging, and improve productivity.
Preferred Qualifications
- Expertise in static timing analysis of multiple interfaces (e.g., SerDes, UCIe) and experience with industry-standard EDA tools such as Cadence Virtuoso and Synopsys Fusion Compiler.
- Knowledge of asynchronous architectures and circuits and familiarity with EDA software development using object-oriented programming languages like Java or C++.
- Demonstrated ability to work collaboratively across cross-functional teams, providing mentorship and guidance to junior engineers.
- Experience in both power-efficient and high-frequency physical design techniques with advanced tools and methodologies.
Join us in shaping the future of computing architectures. Your expertise and ideas will drive groundbreaking innovations in physical design and high-performance silicon solutions.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
As a Physical Design Engineer, you will play a critical role in driving the development of cutting-edge technologies at Intel. You will work hands-on to deliver high-performance physical designs, ensuring the successful integration of advanced semiconductor technologies. Your work will directly impact Intel's product innovation, addressing complex challenges in power, performance, and area optimization to shape the future of computing architectures. From synthesis to sign-off, your contributions will enable Intel to meet ambitious design goals and deliver transformative solutions to the market.
Business Group
This role is part of Intel's Corporate Technology Office (CTO), a dynamic group dedicated to advancing the company's technological leadership and innovation. The group focuses on developing foundational technologies, architectures, and methodologies that drive Intel's product roadmap and enable breakthrough computing solutions. Collaborating with cross-disciplinary teams, the CTO plays a pivotal role in delivering impactful designs that support Intel's broader mission of creating world-changing technology.
Key Responsibilities
- Drive RTL-to-GDS design convergence using advanced synthesis and place-and-route tools targeting performance, power, and area (PPA) goals.
- Deliver block-level physical design, including closure of backend flows, electrical requirements, and enhancing silicon yield.
- Collaborate with CAD and physical design methodology teams to adopt industry-leading tools and optimizations for custom designs.
- Execute physical implementation tasks such as floor planning, bus/pin placement, power/clock distribution, congestion analysis, timing closure, IR drop analysis, and physical verification.
- Debug timing, EM/IR, LVS, and DRC violations, and drive sign-off activities for high-quality silicon production.
- Work closely with custom IP teams to define and optimize memory macros and standard cell libraries to improve overall design efficiency.
- Develop and refine physical design methodologies to enhance workflow and productivity.Qualifications:Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field and 6+ years of hands-on physical design experience OR a Master's degree with 4+ years of relevant experience.
- Demonstrated experience in floor planning, timing constraints definition, synthesis, place-and-route, and achieving product KPIs.
- Proficiency in scripting languages such as Python, Perl, and TCL for design flow automation and debugging.
- Hands-on experience with debugging functional equivalence verification (FEV) and RV reports, including planning and implementing engineering change orders (ECOs).
- Strong understanding of chiplet integration and advanced packaging techniques.
- Experience leveraging AI tools to set up workflows, streamline debugging, and improve productivity.
Preferred Qualifications
- Expertise in static timing analysis of multiple interfaces (e.g., SerDes, UCIe) and experience with industry-standard EDA tools such as Cadence Virtuoso and Synopsys Fusion Compiler.
- Knowledge of asynchronous architectures and circuits and familiarity with EDA software development using object-oriented programming languages like Java or C++.
- Demonstrated ability to work collaboratively across cross-functional teams, providing mentorship and guidance to junior engineers.
- Experience in both power-efficient and high-frequency physical design techniques with advanced tools and methodologies.
Join us in shaping the future of computing architectures. Your expertise and ideas will drive groundbreaking innovations in physical design and high-performance silicon solutions.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 6+ years of hands-on physical design experience, or a Master's degree with 4+ years of relevant experience
- Experience with floorplanning, timing constraints definition, synthesis, place-and-route, and achieving product KPIs
- Proficiency in Python, Perl, and Tcl scripting for design flow automation and debugging
- Experience debugging functional equivalence verification and RV reports, including planning and implementing engineering change orders
- Understanding of chiplet integration and advanced packaging techniques
- Experience leveraging AI tools to establish workflows, streamline debugging, and improve productivity
- Expertise in static timing analysis of multiple interfaces, such as SerDes and UCIe
- Experience with Cadence Virtuoso and Synopsys Fusion Compiler
- Knowledge of asynchronous architectures and circuits
- Familiarity with EDA software development using Java or C++
- Experience with power-efficient and high-frequency physical design techniques using advanced tools and methodologies
- Ability to collaborate across cross-functional teams and mentor junior engineers
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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What We Do
Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside. With more ingenuity and creativity inside, our work is at the heart of countless innovations. From major breakthroughs to things that make everyday life better— they’re all powered by Intel technology. With a career at Intel, you can help make the future more wonderful for everyone.
