Quantum Cryo CMOS Design Enablement

About GlobalFoundries

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Introduction

The Quantum Cryo CMOS Design Enablement (MTS) role is a technical contributor within the Quantum Technology Solutions organization, reporting to the Sr. Manager / Deputy Director of Cryo CMOS Design Enablement. This position supports the development of cryogenic CMOS design enablement capabilities to enable quantum and cryogenic technologies, focusing on translating device and process innovations into usable Process Design Kits (PDKs) and design flows. The role bridges semiconductor device physics, modeling, characterization, and EDA environments to support scalable, manufacturable, and customer-usable cryogenic design solutions.

Job Summary

As a Member of Technical Staff, this role contributes to the development and execution of cryogenic CMOS PDK and design enablement solutions, including modeling, characterization, test chip development, and EDA integration. The engineer will work cross-functionally with device engineering, process development, and design enablement teams to ensure accurate, validated, and usable design collateral for quantum and cryogenic applications, while supporting customer and internal program requirements through data-driven analysis and hands-on technical execution.

Essential Responsibilities

• Contribute to development of cryogenic CMOS PDKs, including compact models, parameter extraction, and validation across temperature regimes.

• Support device modeling efforts by correlating silicon data, simulations, and model behavior to ensure predictive accuracy.

• Develop and execute electrical characterization plans for cryogenic CMOS devices and circuits.

• Design and implement test structures and test sites to support model extraction and validation.

• Contribute to test chip design and evaluation to enable continuous improvement of PDK capabilities.

• Analyze characterization and test data to identify trends, variability, and opportunities for model and design rule improvements.

• Support development and deployment of design flows, model integration, and PDK deliverables within EDA environments.

• Collaborate with EDA vendors to enable modeling, simulation, and design capabilities for cryogenic and quantum applications.

• Work cross-functionally with device, process, integration, and design enablement teams to translate technology into usable design collateral.

• Document methodologies, assumptions, and results to support scalable design enablement and knowledge transfer.

Required Qualifications

• Education: BS or MS in Electrical Engineering, Physics, Applied Physics, or related field

• Years of Experience: 5+ 

• Experience with device modeling, characterization, or test structures

• Familiarity with electrical characterization techniques and data analysis

• Experience working with EDA tools and semiconductor design flows

• Strong analytical, problem solving, and communication skills

Preferred Qualifications

• Experience with cryogenic electronics or low-temperature device behavior

• Exposure to PDK development or compact model implementation

• Experience designing test chips or supporting silicon validation activities

• Familiarity with variability modeling or statistical data analysis

• Experience working with EDA vendors

• Exposure to quantum computing hardware

Expected Salary Range

The exact Salary will be determined based on qualifications, experience and location.