Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.
Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.
Job DescriptionWe are seeking an experienced and highly technical Backend Physical Design Engineer to drive the physical implementation of our next-generation, high-performance SoCs. You will own the complete RTL-to-GDSII flow, focusing heavily on power recovery, clock tree optimization, and pushing aggressive PPA metrics on advanced technology nodes
Key Responsibilities
- RTL-to-GDSII Execution: Own and drive the end-to-end physical design implementation, including floor planning, synthesis, placement, Clock Tree Synthesis (CTS), and routing.
- PPA Optimization: Fine-tune the design to meet stringent Power, Performance, and Area (PPA) targets. Employ advanced techniques like multi-voltage domains, power gating (UPF), and datapath optimization to minimize power while maximizing speed.
- Timing Closure & STA: Drive Static Timing Analysis (STA) across multiple corners and operating modes. Resolve setup/hold violations, signal integrity issues, and clock domain crossing constraints.
- Physical & Formal Verification: Execute Design Rule Checks (DRC), Layout Versus Schematic (LVS), electromigration/IR drop (EMIR) analysis, and Equivalence Checking (LEC/Formality) to ensure design reliability and manufacturability.
- Cross-Functional Collaboration: Work closely with RTL (Frontend), DFT, and Signoff teams to iterate on designs and structural changes for optimal PPA.
- Programming/Scripting: Strong scripting skills in Tcl, Python, or Perl to automate flows and improve design methodologies
- Experience of about 10+ years in Physical design implementation
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Ability to understand design specifications, can contribute to design planning, partitioning, and setup a feasible seed for convergence PD cycle.
- Extensive experience in physical design PPA activities, including floorplanning, placement, clock tree synthesis, routing, and timing closure.
- Good understanding of EDA tools such as Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC, Calibre, Red Hawk.
- Strong understanding of static timing analysis, power analysis, and signal integrity analysis.
- Excellent problem-solving skills and attention to detail.
- Ability to work effectively in a team environment and communicate clearly with cross-functional teams.
- Experience in mentoring and coaching junior engineers is a plus.
Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.
At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.
We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.
Are you ready to join our team and shape the future with us?
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.
Skills Required
- 10+ years experience in physical design implementation
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
- Extensive experience in floorplanning, placement, clock tree synthesis, routing, and timing closure (PPA activities)
- Strong scripting skills in Tcl, Python, or Perl to automate flows
- Good understanding and hands-on experience with EDA tools: Fusion Compiler, Innovus, PrimeTime, Tempus, VCLP, LEC/Formality, Calibre, Red Hawk
- Strong understanding of static timing analysis, power analysis, and signal integrity analysis
- Ability to interpret design specifications, contribute to design planning and partitioning, and set seeds for PD convergence
- Experience with power optimization techniques including multi-voltage domains and power gating (UPF)
- Execute physical and formal verification: DRC, LVS, EMIR/IR drop analysis, equivalence checking (LEC/Formality)
- Excellent problem-solving skills, attention to detail, and clear cross-functional communication
- Experience mentoring and coaching junior engineers
Renesas Electronics Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Renesas Electronics and has not been reviewed or approved by Renesas Electronics.
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Fair & Transparent Compensation — Feedback suggests pay is generally fair-to-good across many roles, with base pay aligned to prevailing market levels in multiple U.S. locations. Engineering and leadership tracks can be competitive on total compensation, reinforcing a sense that pay can meet market expectations in key job families.
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Healthcare Strength — Feedback suggests core medical, dental, and vision coverage is solid and well-regarded by employees. Day-one eligibility in U.S. roles is described, supporting confidence in access and continuity of care.
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Leave & Time Off Breadth — Feedback suggests PTO, paid holidays, sick time, and parental leave provide a comprehensive time-off framework. Company initiatives like Renesas Day and meeting-light Focus Fridays further support time away and balance.
Renesas Electronics Insights
What We Do
We're the world's leading semiconductor manufacturer. Our mission is to make our lives easier and a world that's safer, healthier, greener, and smarter.
