Principal Software Engineer

Reposted 2 Months Ago
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Noida, Gautam Buddha Nagar, Uttar Pradesh, IND
In-Office
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Develop performance models for DDR memory controller architectures, perform architectural analysis, and automate performance metrics generation.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Summary

We are looking for modeling engineers to help develop performance models, perform architectural tradeoff analysis, and enable data driven design decisions for our next generation DDR memory controller architectures that can meet today’s complex SoC and workload requirements. Hardware modelling experience (C++/SystemC/TLM/Python) and computer architecture foundation is desired.

Responsibilities

  • Develop cycle-level performance models in SystemC or C++
  • Correlate performance models to match RTL configurations and traffic conditions
  • Work with Memory Architects to understand feature requirements, architectural specifications and implement in the model
  • Analyze architectural trade-offs (throughput, hardware cost) across different scenarios and architectural choices
  • Develop synthetic memory traffic/traces that are representative of real-world applications (CPU, GPU, DSP, NoC, etc)
  • Develop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks

Required Skills

  • BE/B.Tech ME/M.Tech in ECE, E&TC, CS or similar
  • 5+ years of experience in hardware modeling, functional or performance
  • Strong coding skills in C++, SystemC and Transaction Level Modeling (TLM)
  • Basic understanding of performance principles, Queuing Theory, throughput/latency tradeoffs
We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • BE/B.Tech ME/M.Tech in ECE, E&TC, CS or similar
  • 5+ years of experience in hardware modeling, functional or performance
  • Strong coding skills in C++, SystemC and Transaction Level Modeling (TLM)
  • Basic understanding of performance principles, Queuing Theory, throughput/latency tradeoffs

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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