Job Qualification:
- Experienced Static Timing Analysis (STA) Lead with 12+ years of experience doing STA for SoCs and Blocks.
- He/She should have experience of Multi mode timing constraint development, execution, and final timing signoff for advanced technology nodes.
- He/She will work closely with Architects,Front End,DFT and the PD team to understand design,clocking,timing ,Requirements and lead the writing constraints and closing timing activities
Key Responsibilities
- Constraint Development: Create, validate, and maintain Synopsys Design Constraints (SDC) for block and full-chip levels, covering false paths, multicycle paths, and test modes.
- Timing Signoff: Perform exhaustive timing analysis across multiple corners and modes (MCMM), adhering to process, voltage, and temperature (PVT) variations.
- Violation Debugging: Debug and resolve setup, hold, transition, and path-based violations (PBA).
- Optimization & ECO: Drive timing closure by generating and evaluating timing Engineering Change Orders (ECOs).
- Cross-functional Collaboration: Partner with RTL, physical design, and DFT teams to ensure robust timing integration and refine timing models.
- Tool & Flow Automation: Develop and support implementation flows using industry-standard Electronic Design Automation (EDA) tools and improve script-based automation.
- Debugging timing issues from GLS
- Drive a team of STA engineers.
More information about NXP in India...
#LI-7013Skills Required
- 12+ years of experience doing STA for SoCs and blocks
- Experience in multi-mode timing constraint development, execution, and final timing signoff for advanced technology nodes
- Ability to create, validate, and maintain Synopsys Design Constraints (SDC) at block and full-chip levels
- Perform exhaustive timing analysis (MCMM) across multiple corners and modes considering PVT variations
- Debug and resolve setup, hold, transition, and path-based (PBA) timing violations
- Drive timing closure by generating and evaluating timing ECOs
- Develop and support implementation flows using industry-standard EDA tools and improve script-based automation
- Experience debugging timing issues from gate-level simulation (GLS)
- Experience partnering with RTL, physical design, and DFT teams to refine timing models
- Experience leading and driving a team of STA engineers
What We Do
NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer and more sustainable world through innovation. As a world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 34,500 employees in more than 30 countries and posted revenue of $13.21 billion in 2022. Find out more at www.nxp.com. Privacy Policy: https://www.nxp.com/company/about-nxp/privacy-policy-for-social-media-pages:PRIVACY-POLICY-SOCIAL-MEDIA
