Principal Silicon Engineer

Sorry, this job was removed at 08:48 p.m. (UTC) on Monday, Aug 03, 2026
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5 Locations
In-Office
143K-304K Annually
Expert/Leader
Software • Quantum Computing • Metaverse • Infrastructure as a Service (IaaS)
The Role
Design, verify, and architect PLL cores for SerDes interface IP. Lead timing analysis, simulation, post-layout verification, low-jitter global clock distribution, and coordinate layout, modeling, and post-silicon validation efforts.
Summary Generated by Built In
Overview

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.


As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Interface IP Team team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

 We are looking for a Principal Silicon Engineer to join the team.


#SCHIE


Responsibilities
  • Design and verify PLL cores for custom SerDes interface IP
  • Architecture of the PLL core
  • Review timing reports of critical timing cells inside the PLL core (e.g. digital loop filters & analog-to-digital timing interfaces)
  • Simulation, post-layout verification & co-ordination with layout designers and other engineers on the macro
  • Global clock distribution owner responsible for low jitter clocking for high-speed clocking spines across the SerDes macro
  • Co-ordinate with modeling designers to ensure PLL functionality

Qualifications

Required Qualifications:

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.

Other Requirements:

  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
  • This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be requiredto provide either proof of their country of citizenship or proof of their US. residency or other protected status(e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information.To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Preferred Qualifications:

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR equivalent experience.
  • 1+ year(s) experience working on or leading projects from beginning-to-end.
  • 10+ years of experience in high-speed clocking and PLL design
  • Experience with deep sub-micron nodes and hands on layout optimization experience
  • Ability to review DV waveforms and debug calibration related issues
  • Post silicon validation
  • Python, Perl & other scripting languages for post silicon validation
  • Matlab (Simulink) & modeling
  • Analog Behavioural Modeling (ABM)

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay


This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.



Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Skills Required

  • Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with equivalent years of technical engineering experience (Bachelor's +8 years, Master's +6 years, Doctorate +3 years)
  • Ability to meet Microsoft Cloud Background Check and related security screening requirements
  • Provide proof of citizenship or U.S. residency or other protected status for export-controlled information access
  • 1+ year experience working on or leading projects from beginning-to-end
  • 10+ years of experience in high-speed clocking and PLL design
  • Experience with deep sub-micron nodes and hands-on layout optimization
  • Ability to review DV waveforms and debug calibration related issues
  • Post-silicon validation experience
  • Python, Perl and other scripting languages for post-silicon validation
  • Matlab (Simulink) and modeling experience
  • Analog Behavioural Modeling (ABM) experience

Microsoft Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Microsoft and has not been reviewed or approved by Microsoft.

  • Fair & Transparent Compensation Pay is presented as broadly competitive overall, with clear role/level/location variation and an emphasis on using posted ranges and band information for apples-to-apples comparisons.
  • Retirement Support Retirement benefits are described as a standout, highlighted by a strong 401(k) match structure and immediate vesting, plus additional plan features for tax-advantaged saving.
  • Parental & Family Support Family-oriented benefits are portrayed as a meaningful strength, with substantial paid parental leave and added supports like back-up care and adoption/surrogacy assistance.

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