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The Role
Lead customer and foundry enablement for in-design physical verification solutions covering DRC, fill, and LVS. Deploy, debug, and optimize Innovus and Pegasus/PVS flows for advanced-node designs, validate rule decks, resolve customer issues, collaborate with R&D and field teams, and develop automation that improves verification coverage and turnaround time.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The Product Engineering team works closely with customers, foundries, R&D, and application engineering teams to deliver leading-edge physical verification solutions for advanced semiconductor designs.
Responsibilities
- Work closely with foundries and mutual customers to enable and support in-design Physical Verification (PV) solutions throughout the design implementation flow.
- Serve as a technical expert in Physical Verification methodologies, including Design Rule Checking (DRC), Fill, and Layout Versus Schematic (LVS), with a focus on advanced node technologies.
- Support customers in deploying, debugging, and optimizing in-design PV flows using Cadence implementation and verification technologies, including Innovus and Pegasus/PVS solutions.
- Collaborate with foundries to validate and enhance Physical Verification rule decks and ensure seamless integration into customer design flows.
- Provide technical support and guidance to customers for complex PV-related issues, working both onsite and remotely.
- Interface closely with corporate R&D, field teams, foundries, and customers to identify product enhancements, resolve technical challenges, and improve overall solution quality.
- Develop and drive efficient methodologies and automation flows that improve design productivity, verification coverage, and turnaround time.
Required Qualifications
- 8+ years of professional experience with a Master's degree, or 10+ years with a Bachelor's degree.
- Strong hands-on experience with digital implementation tools, preferably Cadence Innovus.
- In-depth understanding of Physical Verification methodologies, including:DRC (Design Rule Checking) Fill LVS (Layout Versus Schematic)
- Experience supporting physical implementation and signoff flows for advanced technology nodes (16nm/14nm FinFET and below).
- Practical experience debugging and resolving Physical Verification issues in customer design environments.
- Working knowledge of commercial Physical Verification tools such as:Pegasus / PVS Calibre ICV or equivalent solutions.
- Strong communication and customer-facing skills, with the ability to work effectively across customers, foundries, R&D, and field teams.
- Professional proficiency in spoken and written English.
Preferred Qualifications
- Experience with foundry enablement and Physical Verification rule deck development or validation.
- Experience in a design service or customer support organization.
- Scripting or automation experience using Tcl, Python, Perl, or similar languages.
- Familiarity with advanced-node implementation challenges, including DRC closure, fill strategies, and signoff verification methodologies.
Skills Required
- 8+ years of professional experience with a Master's degree
- 10+ years of professional experience with a Bachelor's degree
- Hands-on experience with digital implementation tools, preferably Cadence Innovus
- In-depth understanding of DRC, fill, and LVS physical verification methodologies
- Experience supporting physical implementation and signoff flows for advanced technology nodes, including 16nm/14nm FinFET and below
- Experience debugging and resolving physical verification issues in customer design environments
- Working knowledge of commercial physical verification tools such as Pegasus, PVS, Calibre, ICV, or equivalent
- Strong communication and customer-facing skills
- Ability to work effectively across customers, foundries, R&D, and field teams
- Professional proficiency in spoken and written English
- Experience with foundry enablement and physical verification rule deck development or validation
- Experience in a design service or customer support organization
- Scripting or automation experience using Tcl, Python, Perl, or similar languages
- Familiarity with advanced-node implementation challenges, including DRC closure, fill strategies, and signoff verification methodologies
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
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The Company
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
