Broadcom

Principal Engineer

Reposted One Month Ago

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Hiring Remotely in Zhangjiang, Shanghai Municipality, Shanghai, CHN

Remote

Expert/Leader

Software • Semiconductor • Manufacturing

The Role

Design and implement advanced CMOS ASICs through RTL, synthesis, STA, simulation, physical design, vector generation, and post-prototype test support for 5nm/3nm tapeouts. Drive block and top-level implementation, timing closure, constraint cleanup, and collaborate with customers to optimize designs.

Summary Generated by Built In

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Job Description:

Broadcom Limited offers an excellent opportunity to contribute to a team environment and to grow personal career path. You will be working with internal and external customers to develop state of the art IC solutions utilizing Broadcom’s leading-edge CMOS cell-based ASIC technologies. You will have responsibility for ASIC designs through all of the key development and implementation phases including RTL analysis, synthesis, design optimization, timing verification, simulation, test insertion, physical design, vector generation, and post-prototype test support. Candidates will have opportunity to work on the latest 5nm/3nm designs

Detail design tasks include

Full Chip Synthesis and STA: An ideal candidate should have some background on full chip synthesis flow (DC, DCT, DCG) for 5nm/3nm design tape out. It would be better if the candidate have the experience running full chip STA and constraint clean up flow.

Physical Design Implementation: An ideal candidate having some background in either the Physical Design which includes floor planning, placement, design closure, and DRC & LVS skills.

Overall, candidates are expected to develop the most of above skills. Candidates who have the desire to seek the in-depth and broad technical challenge should apply.

Requirements/Qualifications

- Candidates should have good understanding about ASIC design flow and solid VLSI background.

- Candidates should be able to handle block implementation/top level task independently.

- Tapeout experience in 5nm and blow process design.

- Candidate s should have strong communications and problem solving skills.

- Candidates with experience in any one of following knowledge are a plus

- DFT insertion

- Power/IVD analysis

- DRC/LVS

- Top Floorplan/STA & Low Power

- Candidate is good at Perl/Tcl/Python

Education/Certifications

Preferred Degree: MS Preferred Major: Microelectronics or related discipline

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Skills Required

Good understanding of ASIC design flow and solid VLSI background.
Ability to handle block implementation and top-level tasks independently.
Tapeout experience in 5nm and below process design.
Strong communication and problem solving skills.
Proficiency in Perl, Tcl, and Python.
MS in Microelectronics or related discipline.
Background in full-chip synthesis and STA (DC, DCT, DCG) and constraint cleanup.
Background in physical design implementation (floorplanning, placement, design closure).
Experience with DFT insertion.
Power/IVD analysis experience.
DRC/LVS experience and familiarity with physical verification flows.
Top floorplan/STA and low-power design experience.

Broadcom Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Broadcom and has not been reviewed or approved by Broadcom.

Equity Value & Accessibility — Equity is used broadly through RSUs with quarterly or annual vesting, and an ESPP with a discount and look‑back that can add meaningful upside. Company disclosures show ongoing equity grants, including inducement RSUs tied to acquisitions, underscoring equity’s central role in total rewards.
Retirement Support — A 401(k) plan with a competitive company match and immediate vesting is consistently highlighted, supporting long‑term savings. Tax‑advantaged accounts like HSA/FSA further strengthen the financial wellness toolkit.
Pay Growth & Progression — Compensation ceilings in technical tracks are described as high, with wide ranges and very strong totals for experienced engineers. Sales compensation is also characterized as competitive, supporting attractive on‑target earnings.