Jobs at Broadcom

Execute full physical IC design flow from RTL to tape-out, including synthesis, place-and-route, clock tree synthesis, timing closure, EM/IR analysis, floorplanning, physical verification, and EDA flow/methodology development while collaborating with RTL designers.

Develop and maintain verification environments using SystemVerilog and UVM/OVM; create UVM agents, behavioral models, assertions, coverage; write random and directed tests; analyze/debug simulation failures and coverage; collaborate with design teams to resolve complex verification issues.

Lead and manage customer ASIC programs end-to-end, advise on EDA flows and design best practices, execute physical design checks, assess and mitigate risks, collaborate with cross-functional teams, and support tape-out, bring-up, and production for advanced-node chips.

Lead chip-level digital architecture, own top-level RTL and integration, drive timing/CDC constraints and front-end flows, coordinate cross-discipline teams through tape-out, and mentor engineers while supporting post-silicon bring-up and validation.

Lead full physical IC design flow from RTL to tape-out including synthesis, place-and-route, clock tree synthesis, timing closure, EM/IR analysis, floorplanning, and physical verification. Develop flows and methodologies, collaborate with RTL designers, and perform EDA tool scripting and automation. On-site role at San Jose.

Develop and maintain software solutions for mainframe products, participate in agile development, and engage in code and test plan reviews.

Lead and manage external customer ASIC programs end-to-end, advise on EDA flows and best practices, perform physical design and STA checks, identify and mitigate design risks, coordinate cross-functional teams (test, packaging, fabrication, bring-up), and communicate technical findings to management and business teams.

Develop and maintain advanced verification environments using SystemVerilog/UVM/OVM; design UVM agents and behavioral models; implement assertions and coverage; create random and directed tests; debug simulation failures and analyze coverage; collaborate with design teams on SoC/IP verification.

Lead customer ASIC programs end-to-end—from RFQ through tape-out and production—guiding physical design, STA, test, packaging and EDA flows. Advise customers, execute physical-design checks, assess and mitigate risks, collaborate cross-functionally, and publish best-practice guidance.

Lead and coach software development teams as an Agile leader/Scrum Master, driving continuous improvement, removing impediments, facilitating Scrum/Kanban ceremonies, tracking Agile metrics, collaborating with stakeholders, and fostering high-performing, self-organizing teams.

Pick, pack, and prepare semiconductor shipments to meet scheduled ship dates; verify parts, labels, and packaging; update shipment records and system transactions; coordinate with warehouse/logistics teams; maintain inventory accuracy and resolve shipping discrepancies.

Receive, inspect, and store incoming goods; pick, pack, and prepare orders for dispatch; perform stock counts; follow safety procedures; use RF scanners and basic computer tools; work overtime and assist other areas as needed.

Perform gluing and dressing operations on production components as part of manufacturing operations; follow procedures, safety, and quality standards while supporting production workflow.

The Logic Design Engineer will design and verify high-performance Ethernet switch ASICs, including RTL implementation, verification, and debug analysis, while collaborating with the program lifecycle.

As a PHY Application Engineer, you will support customers on Ethernet PHY products, providing pre-sales and post-sales assistance while addressing complex technical issues and ensuring successful product launches.

The IC Design Engineer will implement mixed-signal ASICs for consumer and satellite projects, involving physical design, verification, and collaboration with various teams. A focus on low-power technologies and extensive tool experience is essential.

Responsible for various DFT aspects, including MBIST, scan insertion, yield improvement, ATE pattern development, and silicon debugging.

The Design Verification Engineer is responsible for verifying networking ASIC designs, developing test plans, implementing test suites, and ensuring completion through various metrics.

This role focuses on developing III-V epitaxy and fabrication processes, optimizing for yield, cost, and production support while using AI/ML tools.

The role involves developing and qualifying III-V epitaxy and wafer fabrication processes, focusing on optimization, yield improvement, and cost control.