Jobs at Broadcom

Leads Broadcom’s local DFT team through ASIC and SoC DFT architecture, insertion, verification, pattern generation, coverage improvement, silicon debug, and yield improvement. Manages DFT resources, collaborates with physical design, STA, manufacturing, test, customers, and global stakeholders, and performs hands-on technical support. Oversees DFT specifications, timing closure, failure analysis, staff development, and product release activities.

Develop and sustain semiconductor wafer-level fabrication processes for prototype and high-volume manufacturing. Responsibilities include wet chemistry and metal deposition process support, equipment troubleshooting, process integration, yield improvement, DOE and SPC analysis, process characterization, documentation, and scaling R&D processes into production. The role collaborates with design and development teams, leads complex improvement projects, and resolves equipment- and process-related issues.

Leads synthesis, static timing analysis, formal verification, low-power implementation, timing closure, and IP release validation for complex mixed-signal ASIC blocks. Develops timing constraints, executes signoff methodologies, performs ECOs, audits release integrity, and automates implementation workflows using scripting. Collaborates across design and physical implementation teams and supports advanced-node silicon tapeouts, with physical design, RTL, and architecture experience considered advantageous.

Plan semiconductor IC demand and supply by reconciling forecasts with Sales and Marketing, creating production and capacity plans, monitoring material requirements, managing outsourced manufacturing partners, securing capacity, allocating production, and controlling inventory to meet delivery, revenue, and days-on-hand targets.

Develop and optimize ATE testing for high-performance XPU ASICs, including test bring-up, silicon characterization, yield improvement, quality screening, and test-time optimization. Lead RMA failure analysis, fault isolation, root-cause debugging, reliability testing, and test hardware management. Collaborate with design, DFT, quality, and global test engineering teams to resolve product issues and improve test coverage.

Develop and optimize automated test equipment solutions for high-performance XPU ASICs. Responsibilities include test bring-up, silicon characterization, yield optimization, guardband tuning, temperature and voltage testing, RMA failure analysis, root-cause debugging, reliability testing, test-file revision control, and load-board management. The role collaborates with design, quality, and global test-engineering teams while supporting Advantest platforms and advanced monolithic and 2.5D/3D packaged devices.

Designs, implements, verifies, and debugs SoC DFT features including scan, MBIST, TAP, LBIST, IO, and SerDes DFT. Generates and validates ATPG test vectors, improves coverage, automates DFT flows, supports tape release and silicon bring-up, and performs failure analysis and yield improvement. Collaborates with physical design, STA, test, manufacturing, customers, and global engineering teams. Requires strong semiconductor DFT, Verilog, ATPG, BIST, scan compression, circuit design, and device physics expertise.

Implements, verifies, and debugs SoC DFT features including scan, MBIST, TAP, LBIST, IO, and SerDes. Generates and validates ATPG test vectors, improves coverage, automates DFT flows, supports tape release and post-silicon ATE bring-up, and performs silicon failure analysis and yield improvement. Collaborates with physical design, STA, test, manufacturing, customer, and global engineering teams on advanced-node ASIC designs.

Supports SoC design-for-test implementation, verification, ATPG pattern generation, coverage improvement, test-vector debugging, silicon bring-up, and test-related design closure. Collaborates with physical design and STA teams while automating DFT flows using scripting and coding skills. The role focuses on Scan, MBIST, TAP, IO integration, Verilog simulation, and ASIC-level test activities under senior engineer guidance.

Designs and validates VMware Kubernetes Service solutions on VMware Cloud Foundation for enterprise customers. Leads technical discovery, workshops, proof-of-concepts, architecture guidance, customer presentations, and modernization proposals. Partners with sales, product management, and engineering to drive platform adoption, address enterprise requirements, and provide feedback for product improvement. The role requires deep Kubernetes and VMware expertise, strong technical communication, and travel up to 50%.

Supports customer-facing portal applications while developing and maintaining Java full-stack applications. Responsibilities include React UI and Spring Boot microservices development, Docker containerization, Kubernetes deployments across GKE and VKS, REST API and database design, CI/CD automation, monitoring, troubleshooting, documentation, user support, training, licensing compliance, and Level 3 incident resolution.

Develop and implement SoC DFT programs from specification through production release. Responsibilities include scan, MBIST, TAP, LBIST, IO, SerDes, ATPG, test-vector generation, simulation, verification, timing closure, silicon bring-up, failure analysis, diagnostics, yield improvement, and customer support. The engineer collaborates with physical design, STA, test, manufacturing, IP, and global customer teams.

Supports FP&A and accounting for semiconductor business units, including forecasting, budgeting, variance analysis, executive reporting, month-end close, journal entries, accruals, fixed asset audits, internal controls, and SOX compliance. Partners with engineering and business leaders on spending, financial modeling, and investment decisions. Helps improve BI dashboards, automate reporting, and optimize financial processes using tools such as Incorta, Oracle ERP, Hyperion, and Essbase.

Designs and implements DFT for SoCs from specification through production release. Responsibilities include scan, MBIST, TAP, LBIST, IO, SerDes, ATPG, test vector generation and verification, test timing closure, silicon bring-up, failure analysis, diagnostics, yield improvement, and customer-return debugging. Collaborates with physical design, STA, test engineering, manufacturing, customers, and global stakeholders.

Designs and implements SoC DFT features including scan, MBIST, boundary scan, LBIST, ATPG, and IJTAG. Generates and debugs test vectors, improves coverage and yield, supports timing closure, and validates silicon on ATE. Performs post-silicon failure analysis and customer-return debugging while collaborating with physical design, test, manufacturing, customers, and global engineering teams.

Industrial Engineer responsible for optimizing high-volume semiconductor manufacturing workflows through operations analysis, time studies, Lean manufacturing, capacity modeling, simulation, and data analytics. The role improves throughput predictability, reduces bottlenecks, develops operational dashboards and trigger charts, integrates manufacturing data from SECS/GEM, MES, and databases, and leads cross-functional continuous improvement initiatives within a 24/7 wafer fab.

Designs and maintains ASIC verification infrastructure, including reusable SystemVerilog and UVM testbenches, verification plans, assertions, reference models, monitors, scoreboards, and regression systems. Develops directed and constrained-random tests, analyzes functional and code coverage, debugs failures, and drives coverage closure for first-pass silicon success. Requires expertise in ASIC verification lifecycles, ARM and AMBA protocols, DSP reference models, and automation scripting.

Bring up complex ASIC and SoC designs on Cadence Palladium emulation platforms, convert RTL into emulation-ready models, support firmware co-verification, perform SystemVerilog/UVM simulation, debug hardware and testbench issues, and automate compilation and regression workflows.

Lead DFT programs from architecture and specification through implementation, verification, tape release, silicon bring-up, debug, and production yield improvement. Implement and verify scan, ATPG, MBIST, boundary scan, LBIST, TAP, IO, and SerDes DFT. Generate and debug test vectors, close test timing with physical design and STA teams, automate DFT flows, support ATE validation, analyze silicon failures, and collaborate with customers and global engineering teams.

Performs SoC DFT specification, implementation, verification, ATPG pattern generation, coverage improvement, timing closure, silicon bring-up, failure analysis, and yield optimization. Integrates scan, MBIST, TAP, LBIST, IO, SerDes, and other DFT features; debugs test vectors and customer-returned parts using ATE. Collaborates with physical design, STA, manufacturing, test, IP, and global customer teams throughout product development and production release.