Jobs at Broadcom

Design, implement, debug, and maintain complex, high-performance enterprise security software. Provide design and code reviews, mentor engineers, write documentation and unit tests, and resolve time-critical customer issues. Leverage AI tools to improve productivity and efficiency while working on authentication, PKI, IAM, and privileged identity use cases.

The Product Engineer will lead cross-functional teams in product qualification, analyze customer returns, and implement improvements for product yield and quality control.

Develops and deploys semiconductor timing sign-off flows using Python, Perl, Tcl, and Unix shell. Responsibilities include EDA flow development for PrimeTime, Tempus, Innovus, and RedHawk; automation; statistical data analysis and modeling; and support for chip design teams. The role requires advanced digital IC design expertise, strong communication, multitasking, problem-solving, and collaboration across projects.

Develop and deploy advanced timing sign-off methodologies for SOC, 3D/2.5D IC, and multi-die designs. Lead EDA flow development using Primetime, Tempus, and Innovus, while applying statistical analysis, silicon technology, testability, and yield expertise. The role requires extensive tapeout and timing sign-off experience, scripting and automation skills, cross-functional collaboration, and autonomous problem solving in a fast-paced engineering environment.

Develop and support AI-driven security products for API management and observability. Own features end to end from incubation through delivery, collaborating with architects and technical leaders. Apply Agile SDLC, CI, secure coding, scalability, testing, performance optimization, documentation, and refactoring practices. Review AI-generated code, troubleshoot complex systems, mentor junior engineers, and establish engineering best practices across development teams.

Operate laboratory equipment to perform process measurements, enter measurement data into systems, inspect materials under a microscope, and prepare items and shipping documents. The role also involves packing, email communication, and completing assigned manufacturing support tasks. Basic computer proficiency in Excel, PowerPoint, and Google Sheets, along with English comprehension, is required.

Design and verify mixed-signal circuits, IO interfaces, analog blocks, and digital wrappers in advanced CMOS technologies. Collaborate with layout and test engineers on physical design, characterization, silicon validation, and test-chip infrastructure. Interface with customers to define requirements and specifications, support ATE and bench testing, and produce datasheets, application notes, and integration guides.

Operates and calibrates epitaxy reactors, supporting fab tools, and wafer testing equipment in a semiconductor manufacturing environment. Performs epitaxy growth and testing functions, follows standard procedures, supports Total Productive Maintenance initiatives, suggests process improvements, escalates equipment issues, and develops basic maintenance and tool changeover skills.

Develop and support AI-driven API management and observability security products using Agile practices. Own features end to end from incubation through delivery, collaborate with architects, ensure software quality, security, scalability, performance, testing, and documentation, and mentor junior engineers. Apply Java, cloud, container, REST, distributed-systems, and modern AI-assisted development techniques while troubleshooting complex systems and reviewing code.

Design and develop memory and circuit blocks at gate or transistor level for AI foundation IP. Responsibilities include circuit simulation, layout extraction, post-layout verification, physical implementation, characterization flow integration, automation scripting, memory model verification, documentation, and silicon test correlation. The role requires expertise in transistor-level behavior, device physics, signal integrity, EM/IR, reliability analysis, simulation tools, and memory circuit design, with DFT and chip integration knowledge preferred.

Design and verify mixed-signal circuits and IO interfaces, including sensors, oscillators, PLLs, LDOs, ADCs, and DACs. Develop RTL wrappers, functional models, timing characterization, test infrastructure, and silicon validation support. Collaborate with layout and test engineers, interface with customers to define requirements, and produce technical documentation such as datasheets, application notes, and integration guides.

Designs and analyzes memory architectures and transistor-level circuit blocks, including layout, physical implementation, post-layout verification, characterization, and behavioral and physical memory models. Develops automation scripts for simulation and verification, documents specifications and timing, supports DFT and chip integration, and creates silicon test plans. The engineer also correlates silicon results with simulations and assists with silicon debug.

Operates epitaxy reactors, supporting tools, and wafer testers in a semiconductor fabrication environment. Calibrates and operates process equipment using standard procedures, supports Total Productive Maintenance initiatives, suggests improvements, escalates equipment issues, and develops skills in basic maintenance tasks during tool changeovers.

Develop and support AI-driven security products for API management and observability. Own features end to end from incubation through delivery, collaborate with architects, apply Agile SDLC, testing, security, scalability, CI, and documentation practices, assess performance, troubleshoot complex systems, mentor junior engineers, and review AI-generated code for quality and architectural alignment.

Designs and validates VMware Kubernetes Service solutions on VMware Cloud Foundation for enterprise customers. Leads technical discovery, workshops, proof-of-concepts, modernization guidance, and customer presentations. Advises on Kubernetes adoption, CI/CD, DevOps, scalability, security, and disaster recovery. Partners with sales, product management, and engineering to develop proposals, create reference architectures, influence product roadmaps, and accelerate platform adoption.

Design and verify mixed-signal circuits and IO interfaces, including sensors, oscillators, PLLs, LDOs, ADCs, and DACs. Develop RTL wrappers, functional models, timing characterization, test infrastructure, and silicon validation support. Collaborate with layout and test engineers, interface with customers, and produce technical documentation. The role requires advanced CMOS design experience, Cadence and SPICE proficiency, physical verification knowledge, and scripting skills.

Supports manufacturing operations focused on QFN testing using Mtod and Inovance. The description provides no additional responsibilities, qualifications, compensation, travel, or clearance requirements.

Design and develop RF hardware products and modules, evaluate materials and reliability, lead cross-functional design and delivery of new products and processes, mentor junior engineers, and resolve complex technical issues using broad engineering and project management expertise.

Lead product definition, design, test, and characterization for isolation products. Drive R&D programs with cross-functional teams, perform yield analysis and failure investigations, establish test setups and ATE testing, and support validation and manufacturing handoff to achieve quality, yield, and reliability targets.

Lead qualification, characterization, and transfer of analog/mixed-signal CMOS ICs from proto to volume production. Perform reliability qualifications (ESD, LU, HTOL, package), PVT product characterization, statistical analysis, and reporting. Drive cross-functional projects for release to production, yield improvement, cost reduction, and customer support. Support package/process qualification, failure analysis, and maintain product quality targets.