Jobs at Broadcom

Integrate IP and verify IP test/debug modes at SoC level. Create RTL, run linting, perform CDC/RDC analysis on RTL and gates, support synthesis, Palladium modeling, STA, zero-delay and SDF simulations, and gate-level simulation. Provide strong debug support and collaborate with global teams.

Customer-facing architect role to design, validate, and deploy VMware Cloud Foundation-based Kubernetes platforms. Lead architecture workshops, PoCs, advanced networking and troubleshooting, create reusable reference architectures, and collaborate with product, engineering, and SI partners to accelerate enterprise adoption.

Design and deliver high-performance flip-chip BGA ASIC packages addressing signal integrity, power integrity, thermal, reliability, and manufacturability. Perform physical layout, manage multiple projects, interface with customers and vendors, and improve design processes and automation.

Lead product strategy and roadmap for VMware Kubernetes Service and Supervisor on VMware Cloud Foundation. Translate customer needs into requirements, partner with engineering/UX/GT M, engage CNCF/open-source communities, drive customer adoption, and represent the product at industry events.

Senior technical solution architect blending systems engineering, product marketing, and customer-facing work to design high-performance SANs and data center fabrics. Leads strategic projects, consults with major customers, partners and OEMs, represents the company at industry forums, and may manage resources with minimal supervision.

Lead product strategy and roadmap for VMware Kubernetes Service and Supervisor within VMware Cloud Foundation. Translate customer needs into product requirements, collaborate with engineering and UX, drive go-to-market and enablement, engage CNCF/open-source communities, and run customer discovery and validation with enterprise customers and partners to shape cloud-native infrastructure for AI/ML and modern workloads.

Drive Broadcom OEM business across Brocade and Emulex product lines in EMEA by aligning with OEMs, expanding revenue, growing pipeline, securing design wins, and building trusted OEM relationships across sales, pre-sales, and marketing.

Perform Wiegand assembly tasks including labeling and inserting wires. Follow production processes, maintain quality and accuracy during assembly, and adhere to safety and workplace procedures.

Perform Weigand assembly tasks including gluing and dressing of components, following assembly procedures, quality and safety standards; basic manual dexterity and adherence to instructions required.

Execute high-quality IC layouts for standard cells, I/O pads, and mixed-signal IP in advanced process nodes. Plan and perform transistor-to-block-level floorplanning, apply design rules and verification (DRC/LVS/ERC/antenna/EM-IR), and collaborate with senior engineers to adopt methodologies and meet project schedules.

Perform UV glue application and housing assembly tasks in a manufacturing environment, following process instructions and quality standards.

Execute high-quality IC layouts for standard cells, I/O pads, and mixed-signal IP in advanced process nodes. Manage floorplanning and transistor-to-block layouts, apply advanced process rules, run physical verification, and collaborate across engineering teams to meet project schedules.

Design and produce high-quality digital and memory layout (standard cells, I/O, memories) using Cadence Virtuoso and Calibre/Hercules verification. Apply process-specific layout rules, floorplan and integrate chips, lead reviews, mentor junior engineers, and meet schedule and verification targets.

Design and execute IC layouts for memory, I/O and standard cells using Cadence Virtuoso and verification tools (Calibre, Hercules). Apply process rules for submicron nodes, perform floor-planning, hierarchy layout, physical verification (LVS/DRC/ERC/antenna/EM), integrate chips, document methodology, and deliver quality layouts on schedule while collaborating with the library team.

Design and implement IC layouts for standard cells, memory and I/O using Cadence tools. Perform floorplanning, hierarchical layout and physical verification (LVS/DRC/ERC/Antenna/EM) with Calibre and Hercules. Deliver high-quality layouts on schedule, adopt new methodologies, lead documentation and technology reviews, and mentor junior engineers.

Design and verify high-quality IC layouts for standard cells, memory, and I/O using Cadence Virtuoso and Calibre/Hercules. Apply advanced process rules, floorplanning, hierarchical layout, and physical verification (LVS/DRC/ERC/antenna/emigration). Lead junior engineers, document layout methodology, and meet project timelines independently.

Lead memory layout design for advanced submicron processes using Cadence and Calibre tools. Own floor-planning, hierarchy layout, verification (LVS/DRC/ERC), scheduling, team leadership, and integration. Document methodologies and adapt flows for new process nodes while training junior engineers and ensuring on-time, high-quality deliverables.

Design and verify high-quality digital and memory layout (standard cell, I/O) using Cadence tools and Calibre/Hercules; perform floorplanning, hierarchy layout, integration, and documentation; lead junior engineers and ensure schedules and process-rule compliance.

Design and verify digital and memory layout for advanced submicron CMOS processes. Apply layout rules, floorplan, complete LVS/DRC/ERC and EM checks, lead junior engineers, and document layout methodology to meet schedule and quality targets.

The IC CAD Engineer will support and enhance CAD tools for Analog/Mixed Signal design, develop automation software, train engineers, and collaborate with EDA vendors.