Principal Engineer

Posted One Month Ago
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Zhubei City, Hsinchu County, TWN
In-Office
Expert/Leader
3D Printing
The Role
Leads GaN power device development for high-efficiency power conversion. Drives device physics, charge-trapping, reliability, architecture, characterization, data analysis, and root-cause investigations. Guides performance, yield, and reliability improvements while collaborating across multidisciplinary teams to accelerate commercialization. Requires extensive GaN semiconductor R&D experience, hands-on trap analysis, technical leadership, English and Chinese fluency, and business travel. TCAD simulation and AEC-Q101 experience are preferred.
Summary Generated by Built In
Job Description

Job Summary

Principal Engineer, GaN Device Engineer, in charge of development of Gallium Nitride (GaN) power devices for high-efficiency power conversion. The candidate will possess expertise in GaN device design & physics to drive high performance/robustness technology. In addition, have an in-depth understanding of trapping mechanisms and relevant characterization techniques with hands-on experience. With strong communication skills in cross-functional teams to drive development path

 

Key Responsibilities

  • ·  Drive technical understanding of GaN device physics, charge trapping mechanisms, and device reliability behavior.
  • ·  Define and evaluate new device architectures to improve performance, robustness, and competitive differentiation.
  • ·  Technical leadership in advanced device characterization, data analysis, and root-cause investigation to drive performance/ yield/ reliability improvement
  • ·  Collaborate with cross-functional teams to guide technology development and accelerate commercialization of GaN products.

Qualifications

[Must]

  • Ph.D. is preferred or M.S. in Electrical Engineering or a related field with 10+ years of semiconductor device R&D experience with major focus on GaN technology.
  • Hands-on experience with characterization techniques and trap analysis: Pulsed I-V (gate-lag and drain-lag), Transient drain current, MOS Interface trap analysis, but not limited as listed.
  • Proven technical leadership and ability to work effectively across multidisciplinary teams.
  • Fluent in both English/Chinese
  • Business travel is required.

[Good-to-Have]

  • Experience with TCAD simulation such as Sentaurus or Silvaco.
  • Reliability failure model and degradation mechanism
  • Familiar with AEC-Q101 standard is “plus”

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Skills Required

  • Ph.D. in Electrical Engineering or a related field, preferred
  • M.S. in Electrical Engineering or a related field with 10+ years of semiconductor device R&D experience focused on GaN technology
  • Hands-on experience with device characterization and trap analysis, including Pulsed I-V, gate-lag, drain-lag, transient drain current, and MOS interface trap analysis
  • Proven technical leadership and ability to work effectively across multidisciplinary teams
  • Fluency in English and Chinese
  • Willingness to travel for business
  • Experience with TCAD simulation tools such as Sentaurus or Silvaco
  • Experience with reliability failure models and degradation mechanisms
  • Familiarity with the AEC-Q101 standard

Renesas Electronics Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Renesas Electronics and has not been reviewed or approved by Renesas Electronics.

  • Fair & Transparent Compensation — Feedback suggests pay is generally fair-to-good across many roles, with base pay aligned to prevailing market levels in multiple U.S. locations. Engineering and leadership tracks can be competitive on total compensation, reinforcing a sense that pay can meet market expectations in key job families.
  • Healthcare Strength — Feedback suggests core medical, dental, and vision coverage is solid and well-regarded by employees. Day-one eligibility in U.S. roles is described, supporting confidence in access and continuity of care.
  • Leave & Time Off Breadth — Feedback suggests PTO, paid holidays, sick time, and parental leave provide a comprehensive time-off framework. Company initiatives like Renesas Day and meeting-light Focus Fridays further support time away and balance.

Renesas Electronics Insights

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The Company
HQ: Tokyo
10,040 Employees

What We Do

We're the world's leading semiconductor manufacturer. Our mission is to make our lives easier and a world that's safer, healthier, greener, and smarter.

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