Principal Engineer, SoC Design

Posted 7 Days Ago
Be an Early Applicant
San Jose, CA, USA
In-Office
250K-310K Annually
Expert/Leader
Artificial Intelligence • Hardware • Semiconductor
The Role
Owns end-to-end SoC implementation from microarchitecture through tapeout and post-silicon validation. Leads design, verification, physical design, DFT/DFX, packaging, and manufacturing coordination; drives timing, power, area, cost, and schedule convergence. Establishes implementation standards and sign-off infrastructure, evaluates IP, manages risks and resources, and mentors engineering teams. Requires deep expertise in SoC front-end design, interconnect, power management, IO, physical design, formal verification, DFT, EDA tools, and scripting.
Summary Generated by Built In

About the Role
We’re looking for a highly experienced SoC Chip Lead to own chip implementation for Kepler’s products. In this high-impact technical leadership role, you’ll lead the design, verification and physical design teams from micro-architecture through tapeout and post-silicon validation.

Responsibilities

  • Own chip implementation end to end: front-end design, verification integration, physical design coordination, DFT/DFX, packaging and manufacturing interaction.

  • Drive design-to-spec execution: lint, CDC, LEC, synthesis, SDC constraints and full design convergence.

  • Evaluate and integrate IP, weighing trade-offs across performance, power, area, cost and schedule.

  • Work with architecture, verification, DFX, physical design, packaging and manufacturing teams so implementation decisions are physically feasible and on schedule.

  • Set and enforce implementation best practices, review standards and sign-off infrastructure.

  • Lead and mentor design and implementation engineers. Drive planning, resourcing and risk mitigation.

Requirements

  • B.Tech/M.Tech/MS in EE, ECE, Computer Engineering or a related field.

  • 15+ years of hands-on SoC front-end design and implementation experience, with multiple successful high-performance tapeouts.

  • Deep expertise in on-chip interconnect, power management and IO subsystem design.

  • Strong working knowledge of physical design: floorplanning, timing convergence and power integrity.

  • Hands-on experience with lint, CDC/RDC, LEC, synthesis, SDC development and formal verification.

  • Solid knowledge of DFT/DFX methods: scan insertion, ATPG, MBIST and JTAG.

  • Skilled with industry-standard EDA tools across the implementation stack.

  • Strong scripting skills (Python, Perl, Tcl, Shell).

  • Excellent leadership and communication skills with a proven ability to drive complex programs in a fast-paced environment.

Nice to Have

  • Experience with 3D innovations

  • Background in high-bandwidth memory subsystem design.

  • Familiarity with AI workloads and their memory demands.

  • Experience with emulation and prototyping platforms.

  • Prior startup experience delivering silicon with lean teams and aggressive schedules.

Compensation and Benefits

Actual compensation will be determined based on factors including, but not limited to, relevant experience, skills, qualifications, education, job responsibilities and work location.

Kepler offers a comprehensive benefits package to eligible employees, including medical, dental and vision coverage, retirement benefits, time off and additional Kepler benefits as applicable. Eligibility and benefit offerings may vary based on employment status and work location.

Equal Employment Opportunity

Kepler is an Equal Opportunity Employer. We provide equal employment opportunities to all applicants and employees and do not discriminate on the basis of race, color, religion, sex, national origin, age, disability, veteran status, or any other characteristic protected under applicable federal, state, or local law.

We believe that different backgrounds, experiences, perspectives and ideas make our team stronger and help our employees, our technology and our community thrive.

Reasonable Accommodation

Kepler is committed to providing reasonable accommodations to qualified individuals with disabilities throughout the application and hiring process. If you need a reasonable accommodation to participate in the application or interview process, please contact us at 408-365-4627 or [email protected].

Fair Chance Hiring

Kepler will consider qualified applicants with criminal histories in accordance with applicable federal, state, and local laws, including the California Fair Chance Act. Applicants are not required to disclose criminal history before a conditional offer of employment except where otherwise permitted or required by applicable law.

Federal Contractor Notice

Kepler is a federal contractor or subcontractor and is committed to its obligations regarding equal employment opportunity. Kepler does not discriminate against qualified individuals on the basis of disability or protected veteran status and takes steps to employ and advance in employment qualified individuals with disabilities and protected veterans.

Skills Required

  • B.Tech, M.Tech, MS, or equivalent degree in Electrical Engineering, Electronics and Communication Engineering, Computer Engineering, or a related field
  • 15+ years of hands-on SoC front-end design and implementation experience
  • Multiple successful high-performance tapeouts
  • Deep expertise in on-chip interconnect, power management, and IO subsystem design
  • Strong working knowledge of physical design, including floorplanning, timing convergence, and power integrity
  • Hands-on experience with lint, CDC/RDC, LEC, synthesis, SDC development, and formal verification
  • Knowledge of DFT/DFX methods, including scan insertion, ATPG, MBIST, and JTAG
  • Experience with industry-standard EDA tools across the implementation stack
  • Strong scripting skills in Python, Perl, Tcl, and Shell
  • Excellent leadership and communication skills with the ability to drive complex programs
  • Experience with 3D innovations
  • Background in high-bandwidth memory subsystem design
  • Familiarity with AI workloads and their memory demands
  • Experience with emulation and prototyping platforms
  • Prior startup experience delivering silicon with lean teams and aggressive schedules

Kepler Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Kepler and has not been reviewed or approved by Kepler.

  • Healthcare Strength — Healthcare coverage, including medical, dental, and vision, is described as comprehensive for eligible employees in company materials. This indicates robust core health benefits even if finer details are not publicly listed.
  • Leave & Time Off Breadth — Paid time off is explicitly included, with references to structured PTO and paid holidays. This suggests time-off policies are a consistent part of the offering across roles.
  • Retirement Support — Retirement plans (such as a 401(k), depending on location and eligibility) are part of the standard package. While the employer match is not publicly specified, the presence of a plan supports long-term savings.

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The Company
HQ: Berkeley, CA
55 Employees
Year Founded: 2018

What We Do

Kepler Computing develops next-generation AI memory and logic using advanced materials, 3D architectures, ferroelectric technologies, and deep semiconductor expertise. Its products target computing’s bandwidth, capacity, energy, and density constraints, particularly for high-throughput, highly interactive AI inference. The company operates as a full-stack semiconductor technology developer spanning memory, logic, chip design, circuits, architecture, advanced packaging, and manufacturing for scalable next-generation compute systems.

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