The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.
Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.
We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.
Join us and shape the future of computing!
Position Overview
You'll be the SoC Lead who owns integration of the full chip, or a major module or subsystem, for a system built around a bandwidth problem most digital teams never face. This is a breadth role: you'll make and defend decisions across DFT, power, timing, and interconnect architecture, with the tapeout scars to know where those decisions bite later. You'll work closely with System Architects, RTL, physical design, and verification leads to close on system-level tradeoffs, and you'll help us scale the design org by hiring and mentoring the specialists under you.
Austin, TX or San Jose, CA. Full-time onsite position.
Key ResponsibilitiesLead integration of the full chip, or a major module/subsystem, including ownership of top-level integration flows.
Make and own cross-domain technical decisions spanning system functionality, DFT, power, timing, and interconnect/data-fabric architecture.
Partner across microarchitecture, RTL, physical design, verification, and DFT to resolve system-level tradeoffs.
Go deep on any domain when needed, staying hands-on with the flow at every level.
Help scale the design org: hire, mentor, and grow engineers across specialty domains (subsystem roles are open now and will continue to open).
Represent chip-level architecture in the context of advanced-node, high-speed, high-bandwidth, low-power, physically large designs.
Principal-level (or equivalent) technical leadership experience at a semiconductor or systems company, with multiple full-chip tapeouts.
Demonstrated breadth across domains: for example, you've closed timing on a block and argued interconnect architecture in the same design cycle.
Deep experience in at least one of: CPU design, or high-speed interconnect / data-fabric design. Interconnect and data-fabric work is especially central to what we're building.
Experience with advanced process nodes, high-bandwidth I/O, and large, physically big subsystem or full-chip designs.
Cadence toolchain experience.
Comfortable being evaluated as either an individual-contributor technical leader or a people manager; we're open to either path for the right person.
Familiarity with AI/ML accelerator or large-scale compute workloads, though not required.
Familiarity with AI-assisted EDA flows in the Cadence toolchain (e.g., Cerebrus) for synthesis, timing closure, or verification.
This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on game-changing technology at the intersection of photonics and AI as part of a collaborative, brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.
Join a team that invests in your future and your well-being. At Neurophos, we offer:
100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
Unlimited PTO. No rigid vacation banks, just a focus on delivery.
401(k) matching and stock option opportunities to ensure our success is your success.
Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.
Skills Required
- Principal-level or equivalent technical leadership experience at a semiconductor or systems company
- Multiple full-chip tapeouts
- Broad experience across domains including timing closure and interconnect architecture
- Deep experience in CPU design or high-speed interconnect/data-fabric design
- Experience with advanced process nodes
- Experience with high-bandwidth I/O
- Experience with large physically sized subsystem or full-chip designs
- Cadence toolchain experience
- Familiarity with AI/ML accelerator or large-scale compute workloads
- Familiarity with AI-assisted Cadence EDA flows such as Cerebrus
- Willingness to work as either an individual-contributor technical leader or people manager
Neurophos Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Neurophos and has not been reviewed or approved by Neurophos.
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Healthcare Strength — Job postings indicate the company covers 100% of base health plan premiums for employees and dependents and contributes to HSAs. Listings also reference dental, vision, and other voluntary coverages.
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Leave & Time Off Breadth — Unlimited PTO is advertised with an emphasis on delivery rather than accruals. Notes in postings suggest clarifying typical usage and any minimums.
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Retirement Support — A 401(k) with employer matching is listed alongside stock option opportunities. This pairing signals structured retirement support in addition to equity participation.
Neurophos Insights
What We Do
Neurophos is an Austin-based semiconductor company developing high-performance, energy-efficient photonic AI inference chips. Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density for an optical system. As AI adoption accelerates, data centers face significant power and scalability challenges. Traditional solutions are struggling to keep up, leading to rapidly rising energy consumption and costs. We’re solving both problems with an OPU that integrates over one million micron-scale optical processing components on a single chip. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving large-scale AI inference performance. We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognized on the EE Times Silicon 100 list for several consecutive years. Join us and shape the future of optical computing!
Why Work With Us
This is an opportunity to work on a game-changing technology at the intersection of photonics and AI. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence.








