Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Principal Digital Design Engineer:
Overview
Join our team as Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.
Key Responsibilities
- Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design.
- Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues.
- Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance.
- Work closely with post-silicon teams to facilitate silicon bring-up and debug.
- Mentor junior engineers to develop their technical skills and expertise.
- Actively contribute to the development and improvement of silicon development processes.
- Drive designs to production, ensuring accountability for quality, schedule, and overall design success.
Required Qualifications:
Education & Experience:
- Bachelor’s degree in electrical engineering or equivalent.
- 8+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
Digital Design Expertise:
- Architecture definition and micro-architecture development
- RTL coding, functional simulation, and synthesis
- Timing closure and gate-level simulation (GLS)
- Design for test (DFT) implementation
- Production experience with advanced CMOS nodes (≤7nm)
Protocols & Integration:
- Deep expertise in at least one high-speed protocol—PCIe, Ethernet, InfiniBand, DDR, or similar
- Third-party IP integration and verification.
- Block-level design ownership from architecture through GDS
Tools & Methodologies:
- Proficiency with Cadence and/or Synopsys digital design flows
- Familiarity with UVM-based verification methodologies.
- Silicon bring-up, debug, and failure analysis expertise
Professional Attributes:
- Strong work ethic with the ability to balance multiple priorities in a dynamic environment
- Excellent communication and collaboration skills; comfortable working cross-functionally with global teams
- Self-directed learner who thrives with minimal supervision and adapts quickly to changing requirements
- Customer-focused mindset with ability to translate business needs into technical excellence
Preferred Qualifications
- Track record of delivering multiple high-performance designs to production in data-center environments
- Hands-on collaboration with embedded firmware teams; deep understanding of firmware development challenges and constraints
- Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
- Proven contributions to design methodology, CAD automation, or design infrastructure to improve productivity or design quality
The base salary range is $185,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Skills Required
- Bachelor's degree in electrical engineering or equivalent
- 8+ years of hands-on experience developing complex SoC or silicon products in server, storage, and/or networking markets
- Experience defining architectures and developing micro-architectures
- Experience with RTL coding, functional simulation, and synthesis
- Experience with timing closure and gate-level simulation
- Experience implementing design-for-test features
- Production experience with advanced CMOS nodes at or below 7nm
- Deep expertise in at least one high-speed protocol, such as PCIe, Ethernet, InfiniBand, or DDR
- Experience integrating and verifying third-party IP
- Block-level design ownership from architecture through GDS
- Proficiency with Cadence and/or Synopsys digital design flows
- Familiarity with UVM-based verification methodologies
- Expertise in silicon bring-up, debugging, and failure analysis
- Track record of delivering multiple high-performance designs to production in data-center environments
- Hands-on collaboration with embedded firmware teams and understanding of firmware development constraints
- Familiarity with embedded processor subsystems such as RISC-V or Arm
- Contributions to design methodology, CAD automation, or design infrastructure improvements
Astera Labs Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.
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Healthcare Strength — Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
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Leave & Time Off Breadth — Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
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Equity Value & Accessibility — Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.
Astera Labs Insights
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
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