Principal Design Engineer

Qualification : BE/ Btech or ME/M.Tech with 10+ Years of Experience

Location:

Position is based in Bangalore.

Job Description:

We are looking for strong technical team lead for IP Integration, subsystem creation, and QA for our SSG IP Integration and QA engineering team.  The role would include working with existing RTL, integration of PHYs and controllers to create sub-systems, and addition of new features. In addition, responsibilities include ensuring various customer configurations are clean as part of verification regressions, and ensuring design is clean for all QA aspects in both Front End and Back End (these includes items like being Timing/LINT/RDC/CDC clean, consistency checks for all IP views etc. A critical part of this role is for the technical lead to also oversee the adoption and roll out of Agentic AI initiatives into all aspects of IP Integration and QA including multi-agent connections in CDNS EDA flows.  They will work closely with various RnD IP leaders and Central Engineering teams around the world to ensure integration and release of IPs are handled on time and with Quality. The lead should also be able to identify constant process improvement and automation to increase the efficiency of the entire RnD IP release process. The role will include people management, and the lead would be responsible for technical and personal growth of their team.  This is a highly visible role as it is serves as a critical final touchpoint from RnD to Customers and our IP teams success hinges on the efficiency and throughput of this team.

Requirements:

• Education:
  • College education in Electronics Engineering or Computer Engineering
• Experience/Abilities:
  • Candidate should be proficient in ASIC development flows like RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT, lint, CDC, LEC etc.
  • Familiarity with Power Flow (UPF/CPF).
  • Experience with functional simulation using Verilog/System Verilog and ability to debug existing Verilog/System Verilog test cases with little or no help from the designer
  • Good in Scripting languages(Shell, Perl, TCL, Python) and automation of design database qualification and packaging. Checks and validation of package consistency.
  • Bug reporting and resolution closure with IP providers
  • Ability to debug synthesis/timing analysis constraints, reports, logs
  • Ability to learn new tools/flows and develop methodology if needed.
• Soft Skills:
  • Ability to build and maintain close relationships with all stake holders such as RnD, Application/Product Engineers, Program Managers, Sales, etc
  • Strong communication skills, both oral and written
  • Need to be results and data driven while being able to pay attention to details
  • Good time management skills to balance multiple high-priority projects.
  • Ability to efficiently lead and train teams
  • Fastidious approach to building automated processes.
  • Strong interpersonal and relationship-building skills.
  • Passionate about quality and ensuring our customer have the best experience
•  Additional Desirable Qualifications:
  • Familiarity with SerDes/DDR/other Design-IP’s & Analog design flows
  • Familiarity with IP release and tracking management systems