Cadence IP Tensilica group is a leading provider of configurable embedded processor technology, with a growing presence in the Automotive Safety market. As a member of the Functional Safety Design Verification Team for Xtensa processors you will be responsible for development and verification of hardware and software safety mechanisms. You will implement simulation or emulation test benches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target safety and product verification goals. You will also assist with fault simulation and analyzing coverage information. You will work closely with the RTL, EDA, and Functional Safety teams. You will develop and deliver functional safety work products, including documentation needed for product safety certification.
Required Skills and Experience:
- 8-10 years of design verification experience
- BS (or higher) in EE/Computer Engineering
- Experience in leading a small team
- Excellent knowledge of computer architecture/micro-architecture and design verification fundamentals
- Expertise with Verilog and popular EDA simulation, SystemVerilog assertions and functional coverage
- Good working knowledge of scripting languages like Perl, Unix shell or similar languages
- Knowledge of technical safety concepts and requirement specifications according to ISO 26262
- Proficient with C language and assembly language
- Excellent written and oral communication skills necessary
- Exposure to debugging netlist/gate level simulation.
- General understanding OS.
- Exposure to MISRA coding guidelines
- Experience in fault simulation tools and methodologies
Skills Required
- 8-10 years of design verification experience
- BS (or higher) in EE/Computer Engineering
- Experience in leading a small team
- Excellent knowledge of computer architecture/micro-architecture and design verification fundamentals
- Expertise with Verilog and popular EDA simulation, SystemVerilog assertions and functional coverage
- Good working knowledge of scripting languages like Perl, Unix shell or similar languages
- Knowledge of technical safety concepts and requirement specifications according to ISO 26262
- Proficient with C language and assembly language
- Excellent written and oral communication skills necessary
- Exposure to debugging netlist/gate level simulation
- General understanding OS
- Exposure to MISRA coding guidelines
- Experience in fault simulation tools and methodologies
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
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What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
