Principal Design Engineer

Posted 18 Days Ago
Be an Early Applicant
Pune, Mahārāshtra, IND
In-Office
Expert/Leader
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Lead physical design initiatives for complex IPs and SoCs (<7nm): perform physical design, timing closure, and physical verification within ASIC flows; use Cadence tools (Genus, Innovus, Quantus, Tempus, PVS, Voltus); address EM/IR and formal verification; develop automation via Makefile/Tcl/Tk/Perl/Python; collaborate across teams and communicate results.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Education: BE/ B Tech/ ME/ M Tech / MS : Expr 6 – 15 (T3/T4)

  • B.Tech/BE/ME/Mtech with hands-on experience physical design , timing closure and physical verification.
  • Exp with ASIC design flow, hierarchical physical design strategies, methodologies and understand deep sub-micron technology issues.
  • Solid knowledge on physical design flow, Timing closure and physical verification. Knowledge of formal verification, EM-IR .
  • Good track records of working on complex IP’s & SoC’s below 7 nm 
  • Power user of Cadence implementation tools, such as Genus, Innovus, Quantus,Tempus, PVS, Voltus.
  • Automation and programming-minded, coding experience in Makefile/Tcl/Tk/Perl/Python.
  • Any AI expr is add on.
  • Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills.
We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • B.E./B.Tech./M.E./M.Tech./M.S. degree
  • 6-15 years relevant experience
  • Hands-on experience in physical design, timing closure, and physical verification
  • Experience with ASIC design flow and hierarchical physical design strategies
  • Knowledge of deep sub-micron technology issues and working on IPs/SoCs below 7 nm
  • Power user of Cadence implementation tools (Genus, Innovus, Quantus, Tempus, PVS, Voltus)
  • Knowledge of formal verification and EM-IR
  • Automation and coding experience (Makefile, Tcl/Tk, Perl, Python)
  • Self-motivated, able to work independently or in a team, excellent verbal and written communication
  • Any AI experience

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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