Role Summary
We are looking for an experienced Principal Analog Design Engineer to drive the design and delivery of high‑speed interface IPs, with a strong emphasis on Die‑to‑Die (D2D) interconnects based on the UCIe standard and advanced package technologies. The role requires hands‑on ownership from architecture through silicon bring‑up, working closely with layout, verification, package, and system teams.
Key Responsibilities
- Architect, design, and deliver high‑speed analog / mixed‑signal circuits for Die‑to‑Die and chiplet‑based systems, including UCIe‑compliant interfaces.
- Own analog blocks for high‑speed interfaces such as clocking, TX/RX front‑ends, termination schemes, biasing, and equalization support circuits.
- Drive architecture definition, feasibility analysis, and design trade‑offs considering signal integrity, power, noise, and packaging parasitics.
- Perform schematic design, simulation, and optimization across PVT corners using industry‑standard EDA tools.
- Work closely with advanced package teams (2.5D / 3D, interposers, organic substrates) to co‑optimize circuit and package design.
- Support layout reviews, parasitic extraction analysis, and post‑layout sign‑off for high‑speed performance.
- Collaborate with AMS verification, digital, and system teams to enable full‑chip integration and validation.
- Participate in silicon bring‑up, debug, and characterization, including correlation with simulation results.
- Contribute to design methodology, checklists, and best practices for high‑speed analog and D2D designs.
Required Qualifications
- Bachelor’s or Master’s degree in Electrical / Electronics Engineering or related field.
- 8+ years of hands‑on experience in analog / mixed‑signal IC design.
- Strong experience with high‑speed interface design (e.g., DDR, PCIe, SerDes, Die‑to‑Die links).
- Solid understanding of UCIe standard concepts, D2D PHY requirements, and chiplet architectures.
- Experience working with advanced packaging technologies and understanding package‑induced effects on high‑speed signaling.
- Proficiency in schematic‑level design, simulation, and debug across PVT corners.
- Strong fundamentals in analog circuit theory, signal integrity, noise analysis, and clocking.
Preferred / Nice‑to‑Have Skills
- Direct hands‑on experience with UCIe PHY design or integration.
- Exposure to AMS verification flows and mixed‑signal simulation environments.
- Experience with post‑silicon debug and correlation.
- Knowledge of power integrity, thermal considerations, and package‑aware design flows.
- Ability to mentor junior engineers and lead technical discussions.
What Success Looks Like
- Robust, scalable UCIe / D2D analog IPs meeting performance, power, and reliability targets.
- Smooth collaboration across design, verification, and packaging teams.
- Predictable execution aligned with project milestones and KPIs / OKRs.
- Strong ownership mindset from architecture to silicon.
Skills Required
- Bachelor's or Master's in Electrical/Electronics Engineering or related field
- 8+ years hands-on analog / mixed-signal IC design experience
- Experience with high-speed interface design (DDR, PCIe, SerDes, Die-to-Die links)
- Solid understanding of UCIe standard concepts, D2D PHY requirements, and chiplet architectures
- Experience with advanced packaging technologies and package-induced effects on high-speed signaling (2.5D/3D, interposers, organic substrates)
- Proficiency in schematic-level design, simulation, and debug across PVT corners using industry-standard EDA tools
- Experience with parasitic extraction, post-layout sign-off, and layout review support for high-speed performance
- Strong fundamentals in analog circuit theory, signal integrity, noise analysis, and clocking
- Direct hands-on experience with UCIe PHY design or integration
- Exposure to AMS verification flows and mixed-signal simulation environments
- Experience with post-silicon debug and correlation between silicon and simulation
- Knowledge of power integrity, thermal considerations, and package-aware design flows
- Ability to mentor junior engineers and lead technical discussions
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
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