Principal Design Engineer ( Layout Design )

Posted Yesterday
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Pune, Mahārāshtra, IND
In-Office
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Lead custom analog layout efforts for DDR IO and other analog IP (op-amps, bandgaps, data converters, LDOs, PLLs, SerDes). Perform physical verification (DRC/LVS/reliability), fix violations, mentor a small team, integrate IP at chip level, and apply DSM methodology for advanced nodes (28nm and below). Scripting/automation is a plus; strong communication, documentation, and problem-solving skills required.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

  • The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
  • Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
  • The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.
  • Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
  • You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Job responsibilities:

Job Description: Layout Design

Job Location : Pune

Work experience : 8- 10 Years or equivalent relevant experience

Responsibilities:

•                 Custom layout design for DDR IO development - Understand design requirements and work closely with the design team and successfully deliver Analog layouts.

•                 Perform physical verifications like DRC/LVS/Reliability and fixing violations

•                 Lead custom layout efforts for DDR IO development - Understand design requirements and work closely with the design team and successfully deliver Analog layouts.

•                 Would be required to lead/mentor a small team of engineers towards a successful IP delivery. 

•                 Perform physical verifications like DRC/LVS/Reliability and fixing violations

Requirements

•                 Hands on layout experience in various analog IP like Opamps, Bandgaps, Dataconverters, LDO and PLL etc.

•                 Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,

•                 Knowledge of various analog layout techniques like matching, shielding etc.,

•                 Good understanding of DSM technology methodology, issues etc.,

•                 Having worked on latest technology nodes, 28nm and below, is desired.

•                 Must have good communication skills and should be team player.

•                 Scripting and automation experience is a plus.

•                 Hands on layout experience in various analog IP like High-speed Analog (Serdes), Data converters, power management and PLL etc.

•                 Understanding layout effects on the circuit such as speed, capacitance, power, and area etc.,

•                 Knowledge of various analog layout techniques, floorplan constraints and IP integration at chip level scenario.

•                 Good understanding of DSM technology methodology, issues etc.,

•                 Having worked on latest technology nodes, 28nm and below, is desired.

•                 Must have good communication skills and should be team player.

•                 Scripting and automation experience is a plus.

•                 Good communication skills, documentation, and presentation skills.

•                 Strong analytical and problem-solving skills.

Qualifications

  • BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent

Behavioral skills required.

  • Must possess strong written, verbal and presentation skills.
  • Ability to establish a close working relationship with both customer peers and management.
  • Explore what’s possible to get the job done, including creative use of unconventional solutions.
  • Work effectively across functions and geographies
  • Push to raise the bar while always operating with integrity.

Regards

Madhu

[email protected]

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • 8-10 years relevant experience
  • BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent
  • Hands-on analog layout experience (opamps, bandgaps, data converters, LDO, PLL, SerDes, high-speed analog)
  • Custom layout design for DDR IO and analog IP delivery
  • Perform physical verifications (DRC/LVS/Reliability) and fix violations
  • Knowledge of analog layout techniques (matching, shielding), floorplan constraints, and IP integration
  • Understanding of layout effects on circuit performance (speed, capacitance, power, area)
  • Good understanding of DSM technology methodology and issues
  • Experience with advanced technology nodes (28nm and below)
  • Scripting and automation experience
  • Leadership/mentoring experience leading a small team
  • Strong communication, documentation, and presentation skills
  • Strong analytical and problem-solving skills

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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