Principal application Engineer – Digital Implementation & Physical Design
Location: Malaysia
Job Overview
We are seeking a Principal application Engineer to support and drive the adoption of Cadence’s digital implementation, physical design, and static verification solutions across key customers in the region.
In this role, you will combine deep hands-on physical design expertise with technical leadership and customer engagement, helping customers achieve optimal performance, power, and area (PPA) on advanced technology nodes. You will work closely with customer design teams, Cadence R&D, Product Engineering influencing methodologies and ensuring successful project execution and tool adoption.
• The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure
• The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high-speed designs at the latest technology nodes.
• The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development.
• The candidate will work closely with RTL design team to ensure successful tapeouts.
Requirement:
• BS/MS in EE/CS with 7+ years of hands-on experience in physical design and verification with prior working experience in 7nm and below technologies.
• Experienced with ASIC design flow, hierarchical physical design strategies, methodologies, and understand deep sub-micron technology issues.
• Solid knowledge on Low Power Design
• Able to assume responsibility for a variety of technical tasks and to work independently
• Self-motivated, able to work as a team player, and good English communication skills
We’re doing work that matters. Help us solve what others can’t.Skills Required
- BS/MS in Electrical Engineering or Computer Science
- 7+ years hands-on experience in physical design and verification
- Prior working experience on 7nm and below technologies
- Experience with ASIC design flow and hierarchical physical design strategies
- Knowledge of deep sub-micron technology issues
- Solid knowledge of Low Power Design methodologies
- Ability to assume responsibility for varied technical tasks and work independently
- Self-motivated team player with good English communication skills
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
-
Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
-
Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
-
Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
.jpeg)
