Physical Design Low Power Verification (VCLP) Lead

Job Details:

Job Description: 

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

Intel is Revolutionizing the Data Center and Server segment. Join us and change the way the world builds servers.

Intel's Data Center and AI group is looking for talented and enthusiastic designers to join our growing team and take part in developing state of the art Servers that will move the data with higher speeds in the Data Center and enrich the lives of every person on Earth.

Who You Are

Your responsibilities include but are not limited to:

• SD/Physical VCLP lead for Xeon projects to ensure multiple power domains are implemented correctly and correct by construction.

• Validation of insertion and connection of isolation cells, power switches, level shifters, retention registers and always-on cells throughout the implementation flow, from initial synthesis to place and route.

• Checks the correct functionality of isolation cells and power switches.

• Work with the Front End UPF, VCLP team to ensure correct by construction of the UPF, Low power Architecture.

• Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.

• Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

• Supporting the team members in closing any design issues.

• Grooming the team members from the technical front.

• Knows how to handle Tape-out interaction with the foundry and worked on post-silicon activities

Qualifications:

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
 

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications

• The candidate must have a Bachelor's degree in Computer/Electrical Engineering or Computer Science and 4+ years of experience -OR- a Master's Degree in Computer/Electrical Engineering or Computer Science and 3+ years of experience -OR- a PhD in Computer/Electrical Engineering or Computer Science

• Experience with owning the full chip level and taping out multiple complex SoCs.

• Leading the project from all the technical aspects right from RTL2GDS2.

• Experience with industry standard Cadence or Synopsys tool suite, and other Sign-off tools from Siemens (Mentor), Ansys etc.

• Must have very good understanding of Full-Chip Level Partitioning, Floor planning, PnR, CTS, different clocking techniques for skew and delay balancing, multiple clock complexity, time budgeting, timing closure techniques, PnR congestion analysis, resolving floor planning issues, UPF (Low power design techniques), resolving formal verification, layout physical problems, understanding and hand-on experience of digital design sign-off tools like and not limited to noise analysis, layout closure, timing and functional eco closure, IR drop analysis etc.

• In-depth knowledge on RTL to GDS2 flow and understanding of basic device physics.

• Experience with internal flow development and understand nuances of Physical Design (Structural Design) flow.

• Minimum 2+ years’ experience with technically leading junior (fresh out of school) to senior/experienced individual contributors.

• Experience with handling developing PDKs (Process Design Kit)

• Working experience with cutting edge technology (5nm or below)

Preferred Qualifications

• Scripting proficiency in PERL, TCL

• Should be able to own any technical task in SoC physical Design work

• Documented experience in technically leading past SoC full chip level physical design execution

• Exposure to various industry standard Physical Design and Sign-Off closure tools

• Knowledge of peer domains to Physical Design, viz., RTL, verification, DFx, post-Si etc.

• Exposure to various industry standard Physical Design and Sign-Off closure tools

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, California, Santa Clara

Additional Locations:US, Colorado, Fort Collins, US, Massachusetts, Hudson, US, Oregon, Hillsboro, US, Texas, Austin

Business group:The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$161,230.00-$227,620.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

The application window for this job posting is expected to end by 03/05/2026