Physical Design Engineer

Physical Design Engineer - Texas Instruments

About the Role: Join Texas Instruments' Connectivity engineering team as a Physical Design Engineer, where you'll play a critical role in delivering high-performance wireless connectivity solutions that power next-generation IoT, automotive, and industrial applications.

What You'll Do:

Physical Implementation

• Floorplanning: Create and optimize chip floorplans to meet performance, power, and area targets
• Placement & Routing: Execute placement optimization and detailed routing for complex SoC designs
• Clock Tree Synthesis (CTS): Design and implement robust clock distribution networks with minimal skew and jitter
• Power Planning: Develop comprehensive power grid strategies including power ring, stripes, and via insertion
• Flow and tool improvements: Work with EDA vendors, TI internal EDA teams to improve flow recipes, implement automations and improve design QoR

Design Verification & Analysis

• Physical Verification: Execute and resolve DRC (Design Rule Check) and LVS (Layout vs. Schematic) violations
• Power management: Execute and verify Lower power checks to ensure power management integrity
• Low power implementation: Conduct dynamic and static power analysis to meet power budgets
• Signal Integrity: Address crosstalk, IR drop, and electromigration issues

Design Optimization

• Performance Optimization: Fine-tune design to meet frequency and timing requirements
• Area Optimization: Minimize die size while maintaining functionality and performance
• Yield Enhancement: Implement design-for-manufacturing (DFM) techniques

Collaboration & Documentation

• Cross-functional Collaboration: Work closely with front-end designers, verification teams, and package engineers
• Documentation: Create and maintain comprehensive design documentation and flow methodologies
• Mentorship: Provide guidance to junior engineers and interns

Growth Opportunities:

• Work on both established connectivity platforms and breakthrough wireless technologies
• Contribute to multiple tape-outs annually across different process nodes
• Influence next-generation connectivity architecture decisions
• Mentorship opportunities with junior engineers and cross-functional collaboration

Why This Role:

• Direct impact on TI's wireless connectivity portfolio performance
• Exposure to diverse wireless standards and emerging technologies
• Opportunity to work with state-of-the-art EDA tools and methodologies
• Be part of innovation initiatives including new wireless technologies for TI

Technical Environment:

• Multiple process technology nodes and design rule sets
• Complex mixed-signal connectivity SoC designs
• Automated flow development and optimization

• Bachelor's / Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field
• 2-5 years of hands-on experience in physical design implementation
• >1 year of hands-on experience on SoC level physical design
• Proficiency with Cadence EDA tools:
  • Innovus: Place and route, timing optimization
  • Conformal Low Power: For power mangement signoff checks
  • PVS: Physical verification
  • Tempus: Not a must have but good to have a working idea of basic timing debugs
• Experience with scripting languages (TCL, Perl, Python, Shell)

• Bachelor's / Master's degree in relevant field
• Familiarity with mixed-signal and analog layout considerations
• Understanding of package and system-level effects

• Power Gating Techniques: Implementation of fine-grain and coarse-grain power gating strategies
• Multi-Voltage Domain Design: Experience with voltage islands, level shifters, and isolation cells
• Clock Gating: Advanced clock gating techniques for dynamic power reduction
• Retention Strategies: Design and implementation of retention flip-flops and memory retention
• Power State Management: Understanding of different power modes (active, idle, sleep, deep sleep)
• Always-On Domain Design: Implementation of always-on power domains and wake-up circuitry

• Physical Design Flow: Complete P&R flow from netlist to GDSII
• Timing Closure: Multi-corner multi-mode timing analysis and optimization
• Power Management: Low-power design techniques including power gating and voltage islands
• Problem Solving: Debug complex timing, power, CTS and physical verification issues

• Design Flow Optimization: Analyze and enhance existing physical design flows for improved efficiency and quality
• Automation Development: Create and maintain automated scripts and tools to streamline repetitive tasks
• Methodology Enhancement: Develop standardized design methodologies and best practices for team adoption
• Quality Metrics: Implement and track key performance indicators (KPIs) for design quality and turnaround time
• Flow Integration: Integrate new EDA tools and technologies into existing design flows
• Runtime Optimization: Optimize tool runtimes and resource utilization for faster design closure
• Cross-Platform Compatibility: Ensure design flows work seamlessly across different compute environments
• Tool Evaluation: Assess new EDA tools and methodologies for potential adoption
• Process Documentation: Create comprehensive flow documentation and user guides
• Continuous Improvement: Identify bottlenecks and implement solutions to improve overall design productivity

• Collaborative team environment with cross-functional projects
• Access to state-of-the-art EDA tools and compute resources
• Opportunity to work on cutting-edge semiconductor technologies
• Multiple platform executions leading to broader learnings and professional development opportunities