About this Opportunity
Join Ericsson's cutting-edge journey to shape the future of 5G networks! As a Physical Design Engineer, you'll work on pioneering digital ASIC designs vital to Ericsson's mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you're passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you.
At Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you'll find a supportive, innovative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom!
We are hiring a Physical Design Engineer to own the physical implementation flow on high-performance, low-power SoC designs at advanced process nodes. Your primary focus will be die-level floorplanning, full-chip place-and-route, and timing-driven physical closure - while also contributing to synthesis and static timing analysis (STA) signoff as secondary responsibilities. You will work closely with RTL design, synthesis, DFT, and verification teams throughout the full design cycle from netlist hand-off to GDSII sign-off.
What you will do:
Floorplanning & Physical Implementation
- Own die-level and block-level floorplanning using Cadence Innovus or Synopsys ICC2 - defining die size, I/O ring placement, power ring topology, and macro placement strategies.
- Perform early floorplan exploration to evaluate area, aspect ratio, and pin assignment trade-offs in collaboration with the architecture and package teams.
- Plan and implement hierarchical design partitioning - define interface timing budgets, feedthrough corridors, and block-level pin constraints for clean top-level integration.
- Coordinate macro placement with memory compilers, analog IP, and hard macros; manage blockage and halo constraints to minimize routing congestion.
- Drive floorplan-driven synthesis feedback loops with the synthesis team; iterate on netlist placement to reduce post-route timing and congestion surprises.
Power Planning & Power Delivery Network (PDN)
- Design and implement the on-chip power delivery network - power rings, power straps, and rail routing - to meet IR drop and electromigration (EM) targets.
- Coordinate with power analysis teams on static and dynamic IR drop budgets; iterate on PDN to achieve sign-off across all power domains.
- Implement and validate multi-voltage domain power structures per UPF/CPF - power switches, isolation cells, level shifters, and always-on logic placement.
- Perform early power grid analysis to identify PDN weaknesses before detailed routing; collaborate with the package team on C4 bump and power delivery co-design.
Place and Route
- Execute full-chip and block-level placement and routing targeting timing, congestion, and power objectives across all MMMC corners.
- Drive timing-driven placement strategies - useful skew, path-specific placement constraints, and pre-CTS timing optimization to reduce hold and setup violations.
- Perform clock tree synthesis (CTS) - define clock tree goals, buffer library selection, skew targets, and clock mesh/shielding strategies for high-frequency designs.
- Manage routing for signal integrity - differential pairs, shielding of sensitive nets, and antenna rule compliance across all metal layers.
- Perform detail routing, via optimization, and metal fill insertion to meet density DRC and sign-off requirements.
Physical Closure
- Drive iterative timing closure - setup and hold - through ECO-driven placement and routing iterations in collaboration with the STA team.
- Perform DRC, LVS, and ERC checks using Synopsys IC Validator or Cadence PVS; own physical verification sign-off to GDSII tape-out.
- Coordinate with power analysis teams to correlate PTPX switching activity maps with IR drop hotspots identified during post-route analysis.
- Own physical implementation QoR metrics - WNS, TNS, congestion, DRC count, and power - and present sign-off status across tape-out milestones.
- Develop and maintain PnR run scripts, methodology documentation, and automation flows in Tcl/Python for reuse across projects and technology nodes.
Synthesis and STA Support
- Support physical-aware synthesis runs using Fusion Compiler - review QoR results and provide floorplan-driven feedback on netlist quality, congestion hotspots, and pre-CTS timing.
- Contribute to STA reviews using PrimeTime (PT) - specifically for timing paths affected by physical implementation changes (CTS, ECO routing, buffer insertion).
The skills you bring:
- B.Tech / M.Tech / M.S. in Electronics Engineering, VLSI Design, Computer Engineering, or a related field with
10+ years in physical implementation, floorplanning, or place-and-route roles - Expert-level proficiency with Cadence Innovus and/or Synopsys ICC2 / Fusion Compiler
- Strong experience in die-level floorplanning, macro placement, and PDN design
- Hands-on clock tree synthesis (CTS) experience across high-frequency, multi-clock designs
- Expertise in timing-driven physical closure and ECO-based hold/setup fixing
- Familiarity with physical verification tools (IC Validator, PVS) and DRC/LVS sign-off
- Working knowledge of synthesis (Fusion Compiler) and STA (PrimeTime)
- Proficiency in Tcl; Python scripting a strong plus
- At least one tape-out on 7nm or below
Nice to have:
- Experience with low-power physical implementation (UPF/CPF, power domain crossings, multi-Vt strategies)
- Knowledge of advanced routing constraints - signal integrity shielding, differential pair routing, antenna fixing
- DFT physical implementation experience - scan chain reordering, BIST placement, and test-mode timing closure
- Exposure to formal equivalence checking (Formality, Conformal) post-ECO
EDA Tools & Environment
- Cadence Innovus, Synopsys ICC2, Fusion Compiler, Synopsys IC Validator, Cadence PVS, PrimeTime, Design Compiler, Tcl / Python
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"All academic credentials must be from recognized and accredited institutions and are further subject to verification."
What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like.We encourage you to consider applying to jobs where you might not meet all the criteria. We recognize that we all have transferrable skills, and we can support you with the skills that you need to develop.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.
Primary country and city: India (IN) || Bangalore
Job details: Developer
Job Stage: Job Stage 6
Primary Recruiter: Ashwini Manda
Hiring Manager: Tommi Kokkola
Skills Required
- B.Tech / M.Tech / M.S. in Electronics Engineering, VLSI Design, Computer Engineering, or related field
- 10+ years in physical implementation, floorplanning, or place-and-route roles
- Expert-level proficiency with Cadence Innovus and/or Synopsys ICC2 / Fusion Compiler
- Strong experience in die-level floorplanning, macro placement, and PDN design
- Hands-on clock tree synthesis (CTS) experience across high-frequency, multi-clock designs
- Expertise in timing-driven physical closure and ECO-based hold/setup fixing
- Familiarity with physical verification tools (IC Validator, PVS) and DRC/LVS sign-off
- Working knowledge of synthesis (Fusion Compiler) and STA (PrimeTime)
- Proficiency in Tcl scripting
- Python scripting experience
- At least one tape-out on 7nm or below
- Experience with UPF/CPF and multi-voltage domain low-power implementation
- Knowledge of advanced routing constraints, signal integrity, and antenna fixes
- DFT physical implementation experience (scan chain reordering, BIST placement, test-mode timing)
- Exposure to formal equivalence checking tools (Formality, Conformal)
What the Team is Saying
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Ericsson Compensation & Benefits Highlights
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Healthcare Strength — Comprehensive medical, dental, vision, and mental‑health options are positioned as core benefits with multiple plan choices in key markets. Official materials explicitly emphasize healthcare breadth as part of “Life at Ericsson.”
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Retirement Support — 401(k) with employer matching in the U.S., pensions in some regions, and broad access to an ESPP indicate strong long‑term financial support. Company filings and AGM materials describe share programs and post‑employment benefits as ongoing pillars of the package.
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Leave & Time Off Breadth — Paid time off, sick leave, holidays, and paid volunteer time are highlighted alongside generous parental leave in various locations. Time‑off entitlements are presented as a strong component of the total rewards offering.
Ericsson Insights
What We Do
Ericsson builds the digital connectivity the world relies on. Our technology underpins the mobile networks, platforms, and systems that billions of people, businesses, and societies depend on every day. We are a global leader in communications technology, delivering mobile network infrastructure, cloud software, and wireless connectivity solutions for service providers and enterprises worldwide. Our networks support connectivity across 180+ countries, helping power everyday communication as well as critical digital services at global scale. Connectivity has evolved far beyond consumer mobile use. Today, nearly 80% of the world’s population accesses the internet via mobile networks, and Ericsson is helping shape what comes next. We are advancing 5G and 5G Advanced, developing network APIs that open connectivity to the global developer ecosystem, and applying automation and AI to make networks more intelligent, efficient, and resilient. Ericsson was the first company to launch live 5G networks on five continents, and our 5G platform is now commercially live in 150+ networks across 60+ countries. We also support more than 36,000 enterprise customers, enabling secure, high-performance connectivity for industries such as manufacturing, aviation, logistics, utilities, and public safety, where reliability and performance are mission critical. Innovation is central to how we work. Ericsson has approximately 28,000 employees in research and development, backed by one of the strongest intellectual property portfolios in the industry with 60,000+ granted patents. Our engineers, researchers, and technologists work across 100+ global R&D sites, helping define how networks evolve and how digital infrastructure is built for the long term. As the world moves toward a mobile-first, AI-powered, and cloud-driven future, connectivity becomes the foundation for digital transformation across every industry. Ericsson is building that foundation, shaping the future of digital connectivity through technology that operates at global scale and supports real-world impact, today and for what comes next.
Why Work With Us
Ericsson is a place for people who want to work on technology that powers everyday life. You’ll contribute to large-scale systems used every day, tackle complex challenges in live environments, and keep developing your skills and career in your own vision.
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