Physical Design Engineer Intern

Posted Yesterday
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Headquarters, AZ, USA
In-Office
Internship
Artificial Intelligence • Computer Vision
The Role
Supports physical design implementation and verification for low-power AI SoCs, working from netlist to GDSII. Responsibilities include floorplanning, automated place and route, static timing analysis, ECO implementation, signal integrity, EM/IR analysis, formal verification, and physical layout verification using LVS, DRC, and DFM at block or full-chip level.
Summary Generated by Built In
AI Vision Processors For Edge ApplicationsOur solutions make cameras smarter by extracting valuable data from high-resolution video streams.

Job Description

The Physical Design Engineer will be an integral part of the physical design team with all aspects of physical design implementation and verification tasks for Ambarella’s cutting edge low power AI SoC from Netlist to GDSII.
The Physical Design Engineer will be responsible for the following areas throughout all phase of SoC implementation process; floor-planning, auto place and route, static timing analysis, eco implementation, signal integrity analysis, EM/IR analysis, formal verification, and physical layout verification (LVS/DRC/DFM) at block and/or full chip level.
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The Company
HQ: Santa Clara, CA
658 Employees
Year Founded: 2004

What We Do

Ambarella (Nasdaq: AMBA) is a leading developer of visual AI products. Our technologies enable a wide variety of human and computer vision applications, including video security, advanced driver assistance systems (ADAS), electronic mirror, drive recorder, driver/cabin monitoring, autonomous driving, and robotic applications. Ambarella’s low-power system on chips (SoCs) offer high-resolution video compression, advanced image processing, and powerful deep neural network processing to enable intelligent cameras to extract valuable data from high-resolution video streams. For more information, please visit www.ambarella.com

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